Registers
http://www.motorola.com/computer/literature 2-27
2
PATOM PPC Address Bus Time-out Machine Check Enable. When
this bit is set, the PATO bit in the ERRST register will be used to assert the
MCHK output to the current address bus master. When this bit is clear,
MCHK will not be asserted.
PDPEM PPCData Parity Error Machine Check Enable. When this bit
is set, the PDPE bit in the ERRST register will be used to assert the MCHK
output to the current address bus master. When this bit is clear, MCHK will
not be asserted.
PERRM PCI Parity Error Machine Check Enable. When this bit is set,
the PERR bit in the ERRST register will be used to assert the MCHK
output to bus master 0. When this bit is clear, MCHK will not be asserted.
SERRM PCI System Error Machine Check Enable. When this bit is
set, the SERR bit in the ERRST register will be used to assert the MCHK
output to bus master 0. When this bit is clear, MCHK will not be asserted.
SMAM PCI Signalled Master Abort Machine Check Enable. When
this bit is set, the SMA bit in the ERRST register will be used to assert the
MCHK output to the bus master which initiated the transaction. When this
bit is clear, MCHK will not be asserted.
RTAM PCI Master Received Target Abort Machine Check
Enable.When this bit is set, the RTA bit in the ERRST register will be
used to assert the MCHK output to the bus master which initiated the
transaction. When this bit is clear, MCHK will not be asserted.
PATOI PPC Address Bus Time-out Interrupt Enable.When this bit is
set, the PATO bit in the ERRST register will be used to assert an interrupt
through the OpenPIC interrupt controller. When this bit is clear, no
interrupt will be asserted.
PDPEI PPC Data Parity Error Interrupt Enable. When this bit is set,
the PDPE bit in the ERRST register will be used to assert an interrupt
through the OpenPIC interrupt controller. When this bit is clear, no
interrupt will be asserted.
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