Renesas H8 Series - Page 19

Rev. 7.00 Mar 10, 2005 page xix of xlii
Item Page Revision (See Manual for Details)
10.2.8 Bit Rate
Register (BRR)
Table 10.5 Maximum
Bit Rate for Each
Frequency
(Asynchronous Mode)
350 Table amended
Setting
OSC (MHz)
φ
φφ
φ (MHz)
Maximum Bit Rate
(bit/s) n N
0.0384
*
0.0192 600 0 0
2 1 31250 0 0
2.4576 1.2288 38400 0 0
4 2 62500 0 0
10 5 156250 0 0
16 8 250000 0 0
20 10 312500 0 0
10.2.8 Bit Rate
Register (BRR)
Table 10.6 Examples
of BRR Settings for
Various Bit Rates
(Synchronous
Mode) (2)
352 Table amended
φ
10 MHz
Bit Rate
(bit/s)
n N Error
200 0 12499 0
250 2 624 0
300 0 8332 0
500 0 4999 0
1K 0 2499 0
2.5K 0 999 0
5K 0 499 0
10K 0 249 0
25K 0 99 0
50K 0 49 0
100K 0 24 0
250K 0 9 0
500K 0 4 0
1M — — —
Notes amended
Notes: The value set in BRR is given by the following equation:
φ
N =
(
4 • 2
2n
• B)
– 1
where B: Bit rate (bit/s)
N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
φ: System clock frequency
n: Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.7.)