Renesas H8 Series - Page 583

Appendix A CPU Instruction Set
Rev. 7.00 Mar 10, 2005 page 541 of 652
REJ09B0042-0700
Mnemonic Operation I H N Z V C
BIOR #xx:3, @aa:8 B C∨(#xx:3 of @aa:8) → C4


























↔↔↔↔↔↔↔
6
BXOR #xx:3, Rd B C⊕(#xx:3 of Rd8) → C2 2
BXOR #xx:3, @Rd B C⊕(#xx:3 of @Rd16) → C4 6
BXOR #xx:3, @aa:8 B C⊕(#xx:3 of @aa:8) → C4 6
BIXOR #xx:3, Rd B C⊕(#xx:3 of Rd8) → C2 2
BIXOR #xx:3, @Rd B C⊕(#xx:3 of @Rd16) → C4 6
BIXOR #xx:3, @aa:8 B C⊕(#xx:3 of @aa:8) → C4 6
BRA d:8 (BT d:8)  PC ← PC+d:8 2 4
BRN d:8 (BF d:8)  PC ← PC+2 2 4
BHI d:8  C ∨ Z = 0 2 4
BLS d:8  C ∨ Z = 1 2 4
BCC d:8 (BHS d:8)  C = 0 2 4
BCS d:8 (BLO d:8)  C = 1 2 4
BNE d:8  Z = 0 2 4
BEQ d:8  Z = 1 2 4
BVC d:8  V = 0 2 4
BVS d:8  V = 1 2 4
BPL d:8  N = 0 2 4
BMI d:8  N = 1 2 4
BGE d:8  N⊕V = 0 2 4
BLT d:8  N⊕V = 1 2 4
BGT d:8 
Z ∨ (N⊕V) = 0 24
BLE d:8  Z ∨ (N⊕V) = 1 24
JMP @Rn  PC ← Rn16 2 4
JMP @aa:16  PC ← aa:16 4 6
JMP @@aa:8  PC ← @aa:8 2 8
BSR d:8  SP−2 → SP 2 6
PC → @SP
PC ← PC+d:8
#xx: 8/16 Rn @Rn @(d:16, Rn) @−Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied No. of States
Addressing Mode/
Instruction Length (bytes)
Condition Code
Operand Size
If
condition
is true
then
PC ←
PC+d:8
else next;
Branching
Condition