RFL Electronics 9780 - Figure 6-3 Receiver Logic Block Diagram (Figure Continues on Next Page)

RFL 9780 RFL Electronics Inc.
April 8, 2003 6-27 (973) 334-3100
Figure 6-3 Receiver logic block diagram (figure continues on next page)
LOGIC ALARM LED
TRIP_INPUT
C14
C13
NORMAL
C25
PRE-TRIP
TIMER
BIPOLAR
TIMER
TRIP OUTPUT
CIRCUIT
BIPOLAR
DETECTOR
PRE-GUARD
TIMER
GUARD HOLD
TIMER
POWER
C20
A
22
GUARD
OUTPUT
CIRCUIT
ALARM
OUTPUT
CIRCUIT
ALARM
TIMER
C21
C23
A
20
GUARD LED
LOGIC _ALM
PWR_ FAIL
A17
PWR_FAIL 2
C16
TO FIG 6-5
GBT/TAG
TIMER
NORMAL
INHIBIT
BLOCK
COMPAR-
ATORS
ACTIVE
50 HZ
FILTER
THRESHOLD
DETECTORS
BLOCKING
LOGIC
30 MS
PULSE
STRETCHER
B NOISE
NORMAL
NOISE_
STRETCH
C29
C17
CE _LOW
CE
HIGH
BLOCK INHIBIT
PRE-
TRIP
GUARD_INPUT
BLOCK
STOP_ALARM
HI SIG
LO SIG
C27
TO UNBLOCKING
FUNCTION
B NOISE
GUARD_VAL
C15
BLK_OUT
TROUT_RLY1
TROUT_SS
TRIP
HOLD
TIMER
HAS_
TRIPPED
B25
STOP
TRIP
LOW_
SIGNAL_
TRIP
(from
unblocking
function)
TRIP RESET BUTTON
DS2
TRIP LED
DS1
DS5
DS4 DS5
SIGNAL_
ENVELOPE
POWER
GDOUT_RLY
GDOUT_SS
POWER
TRIPPED
TRIP_HELD
POWER
LOGIC_ALM