RFL Electronics 9780 - Figure 8-3. Block Diagram of a Basic DDS

RFL 9780 RFL Electronics Inc.
November 1, 2000 8-4 (973) 334-3100
8.3.2 9780 DIRECT DIGITAL SYNTHESIZER
In the RFL 9780, the master clock frequency is a precision 50 MHz signal providing nearly 100 points
per cycle at the maximum output frequency. The phase accumulator is a 32 bit register which provides
over 4 billion possible phase values. This results in a very clean output from the DDS circuit.
All of the DDS functions are performed in a single integrated circuit, U1, which has a differential
current mode output. Resistors R3 and R4 are used for current to voltage conversion. U3C is configured
as a differential amplifier to convert the output of U1 to a single ended signal.
8.3.3 ANTI-ALIASING FILTER
The output of the DDS, after being converted to a single ended signal, is fed into an anti-aliasing filter
formed by U3D. The filter has a cutoff frequency of approximately 600 Khz.
Figure 8-3. Block diagram of a basic DDS
U
P
D
A
T
E
Phase
Register
Sine Lookup
Table
D/A
Converter
A
nalog
Out
Master
Clock
Phase
Step