RFL 9780 RFL Electronics Inc.
April 8, 2003 6-17 (973) 334-3100
6.5 THEORY OF OPERATION
All digital inputs to the Logic Module are buffered before being processed by the A42MX16-PL84I
“Actel” FPGA. The “Actel”, U8, is the heart of the Logic Module. The Actel performs all of the
transmit and receive digital logic control functions. External interface to the Actel consists of eight
banks of switches, one push-button switch, eight LEDs, input and output buffering, and a 2.584 MHz
(color-burst) crystal clock source.
All Logic Module programmable timers and configuration settings are programmed via the eight switch
banks, SW1 through SW8. Each switch bank is strobed in consecutive order by its respective strobe
signal from the Actel. The switch data is latched within the Actel and configures the Logic Module
based upon the switch settings.
The Logic Module utilizes digital timers instead of RC time constants used by its predecessor, the
6780P. All timers are programmable via DIP switches allowing for application specific changes without
having to calculate time-constants or modify hardware.
The Logic Module design can be broken down into two sections: Receiver Logic and Transmitter
Logic. The block diagrams shown in Figures 6-3, 6-5 and 6-6, and the 9780 Logic Module schematic
diagram shown in Figure 6-8 should be referenced to follow the circuit flow throughout the discussion.
6.5.1 RECEIVER LOGIC
The Logic Module receives its input from the modules in the RFL 9780’s receiving section (Sections
11, 12, 13 and 14). It tests the validity of the inputs it receives to optimize security, dependability, and
speed. If the validity tests are successful, it will produce output signals for guard, trip, or logic alarm.
The Logic Module’s guard and trip channels are protected by slow-to-operate, fast-to-release timers.
Short noise bursts cannot cause false trips or guard outputs. A bipolar noise detector provides
protection against signals that shift from guard to trip and back, but not lasting long enough to create an
output from the pre-trip timer
A guard-before-trip/trip-before-guard (GBT/TAG) timer ensures that a noise free guard has been
received for a preset time interval before the trip channel is opened. The trip channel will be closed
again if a valid trip signal is not received within a preset time interval after the guard-input ceases.
However, this added security is unnecessary once a valid trip command has already passed through the
pre-trip timer. A valid trip input will defeat the GBT/TAG timer. Automatic defeat of this timer is
important in many applications, such as the case where a continuous trip signal is used to hold open a
breaker, taking a line out of service. The GBT/TAG timer can only be re-enabled when a solid guard
signal is received for a minimum of 100ms.
Threshold detectors monitor the incoming signal. If the signal level is too low or too high, the trip
channel will be blocked. The low-level signal is optionally applied to the unblocking function of the
Logic Module to generate a low signal trip.
An alarm timer will be activated if an abnormal condition is detected. If the condition persists for the
preset time interval, the alarm circuit will be triggered, and the trip and guard outputs will be blocked
until the abnormal condition has ceased and the alarm drops out.
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