RFL Electronics 9780 - Page 104

RFL 9780 RFL Electronics Inc.
April 8, 2003 6-18 (973) 334-3100
6.5.1.1 PRE-GUARD TIMER
The pre-guard timer ensures that a valid guard input has been received for a preset time interval before
a trip input can be processed. This is done to reduce the possibility of false trips.
Guard commands from the receiving section of the RFL 9780 appear as a logic-high guard input at
edge connector pin C13 (GUARD_INPUT) and can be monitored at TP4. When the guard input goes
high and remains high for a preset time interval, the output of the pre-guard timer will be high. The
output of the pre-guard timer is passed to the guard-hold timer.
6.5.1.2 GUARD-HOLD TIMER
The guard-hold timer ensures that the valid guard input it receives is sustained to prevent brief
instances of guard loss or from causing guard chatter. It accomplishes this by maintaining the guard
output for an additional preset time interval when the valid guard is no longer present, or if a noise
burst were to interrupt the valid guard for a short period.
If the trip-hold timer holds a valid trip, the output of the guard-hold timer (GUARD_VAL) is
immediately blocked, and the guard output will not be sustained for the remainder of the guard-hold
time interval. Note that the guard-hold timer is not used for all applications, in which case, the
GUARD_VAL output would be programmed to go low at the same time as its input goes low. The
GUARD_VAL signal triggers the guard output circuit.
6.5.1.3 GUARD OUTPUT CIRCUIT
The guard-hold timer output signal, GUARD_VAL, will produce a guard output if the pre-guard timer
determines that a valid guard condition exists and a hard block (ALARM) condition does not exist. If
these conditions are met, the transistor will drive the GDOUT_RLY and GDOUT_SS outputs at edge
connectors C21 and C23, energizing the electro-mechanical and solid state guard relays. The active
output of GDOUT_SS is a 32Khz 50% duty-cycle signal. The GUARD indicator DS1 will illuminate to
show that a valid guard input has been received and a guard output has been generated. The guard
outputs will remain energized for the duration of a valid guard, including any preset time interval of the
guard-hold timer.
If an abnormal condition causes the alarm to pickup, the guard output will be blocked until the
abnormal condition ceases and the alarm drops out.
If an under-voltage condition is detected, the PWR_FAIL and/or POWERFAIL2 inputs to the 9780
Logic Module will be logic-low. Both signals in the logic-low state will generate a logic-low POWER
signal to block the guard outputs for the period of the under-voltage condition plus an additional 600
ms.
The status of the guard output circuit is recorded by the sequence of events module (Section 15).