RFL Electronics 9780 - Theory of Operation

RFL 9780 RFL Electronics Inc.
November 1, 2000 7-8 (973) 334-3100
7.5 THEORY OF OPERATION
All digital inputs to the Logic Module are buffered before being processed by the A42MX0984I
“Actel” FPGA. The “Actel”, U8, is the heart of the Tx Logic Module. The Actel performs all of the
transmit digital logic control functions. External interface to the Actel consists of two banks of
switches, one push-button switch, three LEDs, input and output buffering, and a 2.584 MHz (color-
burst) crystal clock source.
All Tx Logic Module configuration settings are programmed via the two switch banks, SW1 and SW2.
Each switch bank is strobed in consecutive order by its respective strobe signal from the Actel. The
switch data is latched within the Actel and configures the Tx Logic Module based upon the switch
settings.
The Logic Module design can be broken down into two sections: Receiver Logic and Transmitter
Logic. The block diagram shown in Figure 7-3 and the 9780 Logic Module schematic diagram shown
in Figure 7-5 should be referenced to follow the circuit flow throughout the discussion.
7.5.1 TRANSMITTER LOGIC
The 9780 Logic Module accepts trip inputs and voice enable signals and uses them to generate control
signals for the transmitter module. It also contains a circuit that monitors the output of the power
amplifier module, and generates a transmitter fail (TX_FAIL) output.
7.5.1.1 TRIP INPUT CIRCUITS
The trip-input circuits accept trip inputs from solid-state input relays at the rear of the 9780 chassis and
passes them to the logic circuits.
SW2-2 selects polarity for TRIPIN_1, and SW2-3 selects polarity for TRIPIN_2. For normally de-
energized contacts, in order for the 9780 to produce a valid trip command, a zero-volt signal must
appear at one or both trip inputs (edge connector pins B21 and C22) depending upon the keying mode.
For normally energized contacts, in order for the 9780 to produce a valid trip command, a TTL level
signal must appear at one or both trip inputs (edge connector pins B21 and C22) depending upon the
keying mode.
The first trip input accepts a signal applied to the TRIPIN_1 input (edge connector pin B21). An RC
network filters out any contact bounce. The output of this filter is applied to a Schmitt trigger. Its output
is passed on to the logic circuits.
The second trip input accepts a signal applied to the TRIPIN_2 input (edge connector pin C22). An RC
network filters out any contact bounce. The output of this filter is applied to a Schmitt trigger. Its
output is passed on to the logic circuits.
TRIPIN_1 is used for tripping in 2F systems, and TRIPIN_2 is used for tripping in 3F systems. A trip
will always override any other condition in any system, with the exception of a 2F-START/STOP
system. TRIPIN_2 is used to override a START applied to TRIPIN_1 in a 2F-START/STOP system.