SBC PCD2 Series - Page 264

Saia-Burgess Controls AG
Manual I/O-modules for PCD1 │ PCD2 series │ Document 27-600 – Release ENG09 │ 2019-05-01
6-121
I/O modules PCD3
PCD3.H150
6
Block diagram
CLK
/CLK
D
/D
A 12
A 13
User PROM
FPGA
(Field Programmable
Gate Array)
PCD bus
Input filter and adaptation 24 V...5 V
Output amplifier 5...32 VDC (Uext)
Clock
/Clock
Data
/Data
Output 12
A 14
A 15
Output 13
Output 14
Output 15
For further details, please refer to manual 26/761 "PCD2.H150 - SSI interface for absolute
encoder".
Watchdog: This module can interact with the watchdog, if it is used on base address 240. In
this case, the last input with address 255 cannot be used.
For details, please refer to the section A4 “Hardware Watchdog”, which describes the correct
use of the watchdog in conjunction with PCD components.