ARM ARM926EJ-S - Page 12

List of Figures
xii Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
Figure 3-4 First-level descriptor ................................................................................................. 3-9
Figure 3-5 Section descriptor ................................................................................................... 3-10
Figure 3-6 Coarse page table descriptor .................................................................................. 3-11
Figure 3-7 Fine page table descriptor ...................................................................................... 3-12
Figure 3-8 Section translation .................................................................................................. 3-14
Figure 3-9 Second-level descriptor .......................................................................................... 3-15
Figure 3-10 Large page translation from a coarse page table ................................................... 3-17
Figure 3-11 Small page translation from a coarse page table ................................................... 3-18
Figure 3-12 Tiny page translation from a fine page table ........................................................... 3-19
Figure 3-13 Sequence for checking faults .................................................................................. 3-26
Figure 4-1 Generic virtually indexed virtually addressed cache ................................................. 4-9
Figure 4-2 ARM926EJ-S cache associativity ........................................................................... 4-10
Figure 4-3 ARM926EJ-S cache Set/Way/Word format ............................................................ 4-11
Figure 5-1 Multi-cycle data side TCM access ............................................................................ 5-8
Figure 5-2 Instruction side zero wait state accesses ................................................................. 5-9
Figure 5-3 Data side zero wait state accesses ........................................................................ 5-10
Figure 5-4 Relationship between DRDMAEN, DRDMACS, DRDMAADDR, DRADDR and DRCS ..
5-11
Figure 5-5 DMA access interaction with normal DTCM accesses ........................................... 5-12
Figure 5-6 Generating a single wait state for ITCM accesses using IRWAIT .......................... 5-13
Figure 5-7 State machine for generating a single wait state .................................................... 5-14
Figure 5-8 Loopback of SEQ to produce a single cycle wait state ........................................... 5-14
Figure 5-9 Cycle timing of loopback circuit .............................................................................. 5-15
Figure 5-10 DMA with single wait state for nonsequential accesses ......................................... 5-16
Figure 5-11 Cycle timing of circuit with DMA and single wait state for nonsequential accesses 5-17
Figure 5-12 Zero wait state RAM example ................................................................................. 5-20
Figure 5-13 Byte-banks of RAM example .................................................................................. 5-21
Figure 5-14 Optimizing for power ............................................................................................... 5-23
Figure 5-15 Optimizing for speed ............................................................................................... 5-24
Figure 5-16 TCM subsystem that uses wait states for nonsequential accesses ........................ 5-25
Figure 5-17 Cycle timing of circuit that uses wait states for non sequential accesses ............... 5-26
Figure 5-18 TCM subsystem that uses the DMA interface ........................................................ 5-27
Figure 5-19 TCM test access using BIST .................................................................................. 5-28
Figure 6-1 Multi-layer AHB system example ............................................................................. 6-8
Figure 6-2 Multi-AHB system example ...................................................................................... 6-9
Figure 6-3 AHB clock relationships .......................................................................................... 6-10
Figure 8-1 Producing a coprocessor clock ................................................................................. 8-2
Figure 8-2 Coprocessor clocking ............................................................................................... 8-2
Figure 8-3 LDC/STC cycle timing ............................................................................................... 8-4
Figure 8-4 MCR/MRC cycle timing ............................................................................................. 8-6
Figure 8-5 Interlocked MCR ....................................................................................................... 8-7
Figure 8-6 Latecanceled CDP .................................................................................................... 8-8
Figure 8-7 Privileged instructions ............................................................................................... 8-9
Figure 8-8 Busy waiting and interrupts ..................................................................................... 8-10
Figure 8-9 CPBURST and CPABORT timing ........................................................................... 8-12
Figure 8-10 Arrangement for connecting two coprocessors ...................................................... 8-14
Figure 12-1 Deassertion of STANDBYWFI after an IRQ interrupt ............................................. 12-2