List of Figures
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. xiii
Figure 12-2 Logic for stopping ARM926EJ-S clock during wait for interrupt .............................. 12-3
Figure B-1 CP15 MRC and MCR bit pattern ............................................................................... B-2
Figure B-2 Rd format for selecting main TLB entry ..................................................................... B-6
Figure B-3 Rd format for accessing MVA tag of main or lockdown TLB entry ............................ B-7
Figure B-4 Rd format for accessing PA and AP data of main or lockdown TLB entry ................ B-8
Figure B-5 Write to the data RAM ............................................................................................. B-10
Figure B-6 Rd format for selecting lockdown TLB entry ........................................................... B-11
Figure B-7 Cache Debug Control Register format .................................................................... B-12
Figure B-8 MMU Debug Control Register format ...................................................................... B-14
Figure B-9 Memory Region Remap Register format ................................................................. B-15
Figure B-10 Memory region attribute resolution .......................................................................... B-17
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