Atmel AVR XMEGA AU series - Register Descriptions - Virtual Port

164
8331B–AVR–03/12
Atmel AVR XMEGA AU
13.15 Register Descriptions – Virtual Port
13.15.1 DIR – Data Direction
• Bit 7:0 – DIR[7:0]: Data Direction Register
This register sets the data direction for the individual pins in the port mapped by VPCTRLA, vir-
tual port-map control register A or VPCTRLB, virtual port-map control register B. When a port is
mapped as virtual, accessing this register is identical to accessing the actual DIR register for the
port.
13.15.2 OUT – Data Output Value
• Bit 7:0 – OUT[7:0]: Data Output value
This register sets the data output value for the individual pins in the port mapped by VPCTRLA,
virtual port-map control register A or VPCTRLB, virtual port-map control register B. When a port
is mapped as virtual, accessing this register is identical to accessing the actual OUT register for
the port.
13.15.3 IN – Data Input Value
• Bit 7:0 – IN[7:0]: Data Input Value
This register shows the value present on the pins if the digital input buffer is enabled. The config-
uration of VPCTRLA, virtual port-map control register A or VPCTRLB, virtual port-map control
register A, decides the value in the register. When a port is mapped as virtual, accessing this
register is identical to accessing the actual IN register for the port.
Bit 76543210
+0x00 DIR[7:0] DIR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x01 OUT[7:0] OUT
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
+0x02 IN[7:0] IN
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000