295
8331B–AVR–03/12
Atmel AVR XMEGA AU
23.3 Clock Generation
The clock used for baud rate generation and for shifting and sampling data bits is generated
internally by the fractional baud rate generator or externally from the transfer clock (XCK) pin.
Five modes of clock generation are supported: normal and double-speed asynchronous mode,
master and slave synchronous mode, and master SPI mode.
Figure 23-2. Clock generation logic, block diagram.
23.3.1 Internal Clock Generation - The Fractional Baud Rate Generator
The fractional baud rate generator is used for internal clock generation for asynchronous modes,
synchronous master mode, and master SPI mode operation. The output frequency generated
(f
BAUD
) is determined by the period setting (BSEL), an optional scale setting (BSCALE), and the
peripheral clock frequency (f
PER
). Table 23-1 on page 296 contains equations for calculating the
baud rate (in bits per second) and for calculating the BSEL value for each mode of operation. It
also shows the maximum baud rate versus peripheral clock frequency. BSEL can be set to any
value between 0 and 4095. BSCALE can be set to any value between -7 and +7, and increases
or decreases the baud rate slightly to provide the fractional baud rate scaling of the baud rate
generator.
When BSEL is 0, BSCALE must also be 0. Also, the value 2
ABS(BSCALE)
must at most be one half
of the minimum number of clock cycles a frame requires. For more details, see ”Fractional Baud
Rate Generation” on page 304.
Baud Rate
Generator
/2
BSEL
/4 /2
Sync
Register
f
OSC
XCK
Pin
txclk
CLK2X
UMSEL [1]
DDR_XCK
0
1
0
1
xcki
xcko
DDR_XCK
rxclk
0
1
1
0
Edge
Detector
PORT_INV
f
BAUD
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