209
8331B–AVR–03/12
Atmel AVR XMEGA AU
The DTI unit consists of four equal dead-time generators, one for each compare channel in
timer/counter 0. Figure 16-3 on page 209 shows the block diagram of one DTI generator. The
four channels have a common register that controls the dead time. The high side and low side
have independent dead-time setting, and the dead-time registers are double buffered.
Figure 16-3. Dead-time generator block diagram.
As shown in Figure 16-4 on page 209, the 8-bit dead-time counter is decremented by one for
each peripheral clock cycle, until it reaches zero. A nonzero counter value will force both the low
side and high side outputs into their OFF state. When a change is detected on the WG output,
the dead-time counter is reloaded according to the edge of the input. A positive edge initiates a
counter reload of the DTLS register, and a negative edge a reload of DTHS register.
Figure 16-4. Dead-time generator timing diagram.
16.5 Pattern Generation
The pattern generator unit reuses the DTI registers to produce a synchronized bit pattern across
the port it is connected to. In addition, the waveform generator output from compare channel A
(CCA) can be distributed to and override all the port pins. These features are primarily intended
for handling the commutation sequence in brushless DC motor (BLDC) and stepper motor appli-
Dead Time Generator
Edge Detect
BV BV
DQ
= 0
DTLSBUF
DTLS
DTHSBUF
DTHS
"DTLS"
(To PORT)
"DTHS"
(To PORT)
Counter
EN
LOAD
WG output
"dti_cnt"
"WG output"
"DTLS"
"DTHS"
t
DTILS
t
DTIHS
T
t
P
To Next Page
Loading...
Need help?
General
