427
8331B–AVR–03/12
Atmel AVR XMEGA AU
Figure 32-14. PDI instruction set summary.
32.6 Register Description - PDI Instruction and Addressing Registers
The PDI instruction and addressing registers are internal registers utilized for instruction decod-
ing and PDIBUS addressing. None of these registers are accessible as registers in a register
space.
32.6.1 Instruction Register
When an instruction is successfully shifted into the physical layer shift register, it is copied into
the instruction register. The instruction is retained until another instruction is loaded. The reason
for this is that the REPEAT command may force the same instruction to be run repeatedly,
requiring command decoding to be performed several times on the same instruction.
32.6.2 Pointer Register
The pointer register is used to store an address value that specifies locations within the PDIBUS
address space. During direct data access, the pointer register is updated by the specified num-
ber of address bytes given as operand bytes to an instruction. During indirect data access,
0 0
LDS
0
Size A
Size B
Cmd
0 1 0
STS
1 0 0
LDCS
CS Address
1 1 0
STCS
1 1 0 0 0
KEY
1
1 0
0 0
0
REPEAT
1
Size B
LDS
STS
ST
0
1
0
0
0
1
1 1
LD
0
0
0
0
Cmd
LDCS (LDS Control/Status)
STCS (STS Control/Status)
KEY
10
0
1
1 1
REPEAT
1
1
1
1
0 0
Size B - Data size
Byte
3 Bytes
Long (4 Bytes)
0
10
0
0
1
1 1
Word (2 Bytes)
CS Address (CS - Control/Status reg.)
0 00 Register 0
Register 2
Reserved
Register 1
0
0
00
1
0 10 0
0 10 1
Reserved1 11 1
......
0
0
Size A - Address size (direct access)
Byte
3 Bytes
Long (4 Bytes)
0
10
0
0
1
1 1
Word (2 Bytes)
0
0
LD
1
Ptr Size A/B Cmd
0 1 1
ST
0
0
0
0
Ptr - Pointer access (indirect access)
*(ptr)
ptr
ptr++ - Reserved
0
10
0
0
1
1 1
*(ptr++)
00
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