Atmel AVR XMEGA AU series User Manual

286
8331B–AVR–03/12
Atmel AVR XMEGA AU
21.11 Register Summary - TWI
21.12 Register Summary - TWI Master
21.13 Register Summary - TWI Slave
21.14 Interrupt Vector Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRL – – – – – SDAHOLD EDIEN 274
+0x01 MASTER Offset address for TWI Master
+0x08 SLAVE Offset address for TWI Slave
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRLA INTLVL[1:0] RIEN WIEN ENABLE – – –275
+0x01 CTRLB
– – – – TIMEOUT[1:0] QCEN SMEN 275
+0x02 CTRLC
– – – – – ACKACT CMD[1:0] 276
+0x03 STATUS RIF WIF CLKHOLD RXACK ARBLOST BUSERR BUSSTATE[1:0] 277
+0x04 BAUD BAUD[7:0] 278
+0x05 ADDR ADDR[7:0] 279
+0x06 DATA DATA[7:0] 279
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRLA INTLVL[1:0] DIEN APIEN ENABLE PIEN TPMEN SMEN 280
+0x01 CTRLB – – – – – ACKACT CMD[1:0] 281
+0x02 STATUS DIF APIF CLKHOLD RXACK COLL BUSERR DIR AP 282
+0x03 ADDR ADDR[7:0] 283
+0x04 DATA DATA[7:0] 284
+0x05 ADDRMASK ADDRMASK[7:1] ADDREN 284
Table 21-10. TWI interrupt vectors and their word offset addresses.
Offset Source Interrupt Description
0x00 SLAVE_vect TWI slave interrupt vector
0x02 MASTER_vect TWI master interrupt vector

Atmel AVR XMEGA AU series Specifications

General

Brand	Atmel
Model	AVR XMEGA AU series
Category	Microcontrollers
Language	English