408
8331B–AVR–03/12
Atmel AVR XMEGA AU
31. IEEE 1149.1 JTAG Boundary Scan Interface
31.1 Features
• JTAG (IEEE Std. 1149.1-2001 compliant) interface
• Boundary scan capabilities according to the JTAG standard
• Full scan of all I/O pins
• Supports the mandatory SAMPLE, IDCODE, PRELOAD, EXTEST, and BYPASS instructions
• Supports the optional HIGHZ and CLAMP instructions
• Supports the AVR-specific PDICOM instruction for accessing the PDI
31.2 Overview
The JTAG interface is mainly intended for testing PCBs by using the JTAG boundary scan capa-
bility. Secondarily, the JTAG interface is used to access the Program and Debug Interface (PDI)
in its optional JTAG mode.
The boundary scan chain has the capability of driving and observing the logic levels on I/O pins.
At the system level, all microcontroller or board components having JTAG capabilities are con-
nected serially by the TDI/TDO signals to form a long shift register. An external controller sets up
the devices to drive values at their output pins, and observes the input values received from
other devices. The controller compares the received data with the expected result. In this way,
boundary scan method provides a mechanism for testing the interconnections and integrity of
components on printed circuit boards by using only the four test access port (TAP) signals.
The IEEE Std. 1149.1-2001 defined mandatory JTAG instructions, IDCODE, BYPASS, SAM-
PLE/ PRELOAD, and EXTEST, together with the optional CLAMP and HIGHZ instructions can
be used for testing the printed circuit board. Alternatively, the HIGHZ instruction can be used to
place all I/O pins in an inactive drive state, while bypassing the boundary scan register chain of
the chip.
The AVR-specific PDICOM instruction makes it possible to use the PDI data register as an inter-
face for accessing the PDI for programming and debugging. This provides an alternative way to
access internal programming and debugging resources by using the JTAG interface. For more
details on PDI, programming, and on-chip debugging, refer to ”Program and Debug Interface” on
page 415.
The JTAGEN fuse must be programmed and the JTAGD bit in the MCUCR register must be
cleared to enable the JTAG interface and TAP. See ”FUSEBYTE4 – Fuse Byte4” on page 32,
and ”MCUCR – Control register” on page 48 for more details.
When using the JTAG interface for boundary scan, the JTAG TCK clock frequency can be
higher than the internal device frequency. A system clock in the device is not required for bound-
ary scan.
31.3 TAP - Test Access Port
The JTAG interface requires and uses four device I/O pins. In JTAG terminology, these pins
constitute the test access port,or TAP. These pins are:
• TMS: Test mode select. The pin is used for navigating through the TAP-controller state
machine
• TCK: Test clock. This is the JTAG clock signal, and all operation is synchronous to TCK
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