83
8331B–AVR–03/12
Atmel AVR XMEGA AU
7. System Clock and Clock Options
7.1 Features
• Fast start-up time
• Safe run-time clock switching
• Internal oscillators:
– 32MHz run-time calibrated oscillator
– 2MHz run-time calibrated oscillator
– 32.768kHz calibrated oscillator
– 32kHz ultra low power (ULP) oscillator with 1kHz output
• External clock options
– 0.4MHz - 16MHz crystal oscillator
– 32.768kHz crystal oscillator
– External clock
• PLL with 20MHz - 128MHz output frequency
– Internal and external clock options and 1x to 31x multiplication
– Lock detector
• Clock prescalers with 1x to 2048x division
• Fast peripheral clocks running at 2 and 4 times the CPU clock
• Automatic run-time calibration of internal oscillators
• External oscillator and PLL lock failure detection with optional non-maskable interrupt
7.2 Overview
XMEGA devices have a flexible clock system supporting a large number of clock sources. It
incorporates both accurate internal oscillators and external crystal oscillator and resonator sup-
port. A high-frequency phase locked loop (PLL) and clock prescalers can be used to generate a
wide range of clock frequencies. A calibration feature (DFLL) is available, and can be used for
automatic run-time calibration of the internal oscillators to remove frequency drift over voltage
and temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt
and switch to the internal oscillator if the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled.
After reset, the device will always start up running from the 2MHz internal oscillator. During nor-
mal operation, the system clock source and prescalers can be changed from software at any
time.
Figure 7-1 on page 84 presents the principal clock system in the XMEGA family of devices. Not
all of the clocks need to be active at a given time. The clocks for the CPU and peripherals can be
stopped using sleep modes and power reduction registers, as described in ”Power Management
and Sleep Modes” on page 105.
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