78
8331B–AVR–03/12
Atmel AVR XMEGA AU
• Set the period register of the timer/counter to ('line count' * 4 - 1), the line count of the
quadrature encoder.
• Enable the timer/counter without clock prescaling.
The angle of a quadrature encoder attached to QDPH0, QDPH90 (and QINDX) can now be read
directly from the timer/counter count register. If the count register is different from BOTTOM
when the index is recognized, the timer/counter error flag is set. Similarly, the error flag is set if
the position counter passes BOTTOM without the recognition of the index.
6.8 Register Description
6.8.1 CHnMUX – Event Channel n Multiplexer register
• Bit 7:0 – CHnMUX[7:0]: Channel Multiplexer
These bits select the event source according to Table 6-3. This table is valid for all XMEGA
devices regardless of whether the peripheral is present or not. Selecting event sources from
peripherals that are not present will give the same result as when this register is zero. When this
register is zero, no events are routed through. Manually generated events will override CHnMUX
and be routed to the event channel even if this register is zero.
Bit 76543210
CHnMUX[7:0] CHnMUX
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 00000000
Table 6-3. CHnMUX[7:0] bit settings.
CHnMUX[7:4] CHnMUX[3:0] Group Configuration Event Source
0000 0000
None (manually generated events
only)
0000 0001 (Reserved)
0000 0 0 1 X (Reserved)
0000 0 1 X X (Reserved)
0000 1000RTC_OVF RTC overflow
0000 1001RTC_CMP RTC compare match
0000 1010
USB start of frame on CH0
(2)
USB error on CH1
(2)
USB overflow on CH2
(2)
USB setup on CH3
(2)
0000 1 0 1 X (Reserved)
0000 1 1 X X (Reserved)
0001 0000ACA_CH0 ACA channel 0
0001 0001ACA_CH1 ACA channel 1
0001 0010ACA_WIN ACA window
0001 0011ACB_CH0 ACB channel 0
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