Name: Atmel AVR XMEGA AU series
Brand: Atmel
Rating: 4 (1 reviews)

To Next Page

To Previous Page

8331B–AVR–03/12

Atmel AVR XMEGA AU

5.12 Interrupts

The DMA controller can generate interrupts when an error is detected on a DMA channel or

when a transaction is complete for a DMA channel. Each DMA channel has a separate interrupt

vector, and there are different interrupt flags for error and transaction complete.

If repeat is not enabled, the transaction complete flag is set at the end of the block transfer. If

unlimited repeat is enabled, the transaction complete flag is also set at the end of each block

transfer.

1 About the Manual2
- Reading the Manual2
- Resources2
- Recommended Reading2
2 Overview3
3 Avr Cpu7
- Features7
- Overview7
- Architectural Overview7
- ALU - Arithmetic Logic Unit8
- Program Flow9
- Instruction Execution Timing9
- Status Register10
- Stack and Stack Pointer10
- Register File11
- RAMP and Extended Indirect Registers12
- Accessing 16-Bit Registers13
- Configuration Change Protection13
- Fuse Lock14
- Register Descriptions15
- Register Summary19
4 Memories20
- Features20
- Overview20
- Flash Program Memory21
- Fuses and Lockbits22
- Data Memory23
- Internal SRAM23
- Eeprom23
- I/O Memory24
- External Memory24
- Data Memory and Bus Arbitration24
- Memory Timing25
- Device ID and Revision25
- JTAG Disable25
- I/O Memory Protection25
- Register Description - NVM Controller26
- Register Descriptions - Fuses and Lock Bits31
- Register Description - Production Signature Row37
- Register Description - General Purpose I/O Memory46
- Register Description - External Memory46
- Register Descriptions - MCU Control47
- Register Summary - NVM Controller51
- Register Summary - Fuses and Lockits51
- Register Summary - Production Signature Row52
- Register Summary - General Purpose I/O Registers53
- Register Summary - MCU Control53
- Interrupt Vector Summary - NVM Controller53
5 DMAC - Direct Memory Access Controller54
- Features54
- Overview54
- DMA Transaction55
- Transfer Triggers56
- Addressing56
- Priority between Channels56
- Double Buffering57
- Transfer Buffers57
- Error Detection57
- Software Reset57
- Protection57
- Interrupts58
- Register Description - DMA Controller59
- Register Description - DMA Channel61
- Register Summary - DMA Controller70
- Register Summary - DMA Channel70
- DMA Interrupt Vector Summary70
6 Event System71
- Features71
- Overview71
- Events72
- Event Routing Network74
- Event Timing76
- Filtering76
- Quadrature Decoder76
- Register Description78
- Register Summary82
7 System Clock and Clock Options83
- Features83
- Overview83
- Clock Distribution85
- Clock Sources85
- System Clock Selection and Prescalers87
- PLL with 1X-31X Multiplication Factor88
- DFLL 2Mhz and DFLL 32Mhz89
- PLL and External Clock Source Failure Monitor90
- Register Description - Clock92
- Register Description - Oscillator96
- Register Description - DFLL32M/DFLL2M101
- Register Summary - Clock104
- Register Summary - Oscillator104
- Register Summary - DFLL32M/DFLL2M104
- Oscillator Failure Interrupt Vector Summary104
8 Power Management and Sleep Modes105
- Features105
- Overview105
- Sleep Modes105
- Power Reduction Registers107
- Minimizing Power Consumption107
- Register Description - Sleep109
- Register Description - Power Reduction109
- Register Summary - Sleep112
- Register Summary - Power Reduction112
9 Reset System113
- Features113
- Overview113
- Reset Sequence114
- Reset Sources115
- Register Description119
- Register Summary120
10 Battery Backup System121
- Features121
- Overview121
- Battery Backup System122
- Configuration123
- Operation123
- Register Description125
- Register Summary127
11 WDT - Watchdog Timer128
- Features128
- Overview128
- Normal Mode Operation128
- Window Mode Operation129
- Watchdog Timer Clock129
- Configuration Protection and Lock130
- Registers Description130
- Register Summary133
12 Interrupts and Programmable Multilevel Interrupt Controller134
- Features134
- Overview134
- Operation134
- Interrupts135
- Interrupt Level138
- Interrupt Priority138
- Interrupt Vector Locations140
- Register Description141
- Register Summary142
13 O Ports143
- Features143
- Overview143
- I/O Pin Use and Configuration144
- Reading the Pin Value147
- Input Sense Configuration148
- Port Interrupt149
- Port Event150
- Alternate Port Functions150
- Slew Rate Control151
- Clock and Event Output151
- Multi-Pin Configuration152
- Virtual Ports152
- Register Descriptions - Ports153
- Register Descriptions - Port Configuration159
- Register Descriptions - Virtual Port164
- Register Summary - Ports166
- Register Summary - Port Configuration166
- Register Summary - Virtual Ports166
- Interrupt Vector Summary - Ports167
14 TC0/1 - 16-Bit Timer/Counter Type 0 and 1168
- Features168
- Overview168
- Block Diagram170
- Clock and Event Sources171
- Double Buffering171
- Counter Operation172
- Capture Channel175
- Compare Channel177
- Interrupts and Events181
- DMA Support181
- Timer/Counter Commands181
- Register Description182
- Register Summary192
- Interrupt Vector Summary192
15 TC2 - 16-Bit Timer/Counter Type 2193
- Features193
- Overview193
- Clock Sources194
- Counter Operation195
- Compare Channel196
- Interrupts and Events197
- DMA Support198
- Timer/Counter Commands198
- Register Description199
- Register Summary205
- Interrupt Vector Summary205
16 Awex - Advanced Waveform Extension206
- Features206
- Overview206
- Port Override207
- Dead-Time Insertion208
- Pattern Generation209
- Fault Protection210
- Register Description212
- Register Summary216
17 Hi-Res - High-Resolution Extension217
- Features217
- Overview217
- Register Description218
- Register Summary218
18 RTC - Real-Time Counter219
- Features219
- Overview219
- Register Descriptions221
- Register Summary226
- Interrupt Vector Summary226
19 RTC32 - 32-Bit Real-Time Counter227
- Features227
- Overview227
- Register Descriptions229
- Register Summary234
- Interrupt Vector Summary234
20 USB - Universal Serial Bus Interface235
- Features235
- Overview235
- Operation237
- SRAM Memory Mapping240
- Clock Generation241
- Ping-Pong Operation242
- Multipacket Transfers243
- Auto Zero Length Packet244
- Transaction Complete FIFO244
- Interrupts and Events245
- VBUS Detection247
- On-Chip Debug247
- Register Description - USB248
- Register Description - USB Endpoint255
- Register Description - Frame260
- Register Summary - USB Module261
- Register Summary - USB Endpoint261
- Register Summary - Frame261
- USB Interrupt Vector Summary261
21 TWI - Two-Wire Interface262
- Features262
- Overview262
- General TWI Bus Concepts263
- TWI Bus State Logic268
- TWI Master Operation269
- TWI Slave Operation271
- Enabling External Driver Interface273
- Register Description - TWI274
- Register Description - TWI Master275
- Register Description - TWI Slave280
- Register Summary - TWI286
- Register Summary - TWI Master286
- Register Summary - TWI Slave286
- Interrupt Vector Summary286
22 SPI - Serial Peripheral Interface287
- Features287
- Overview287
- Master Mode288
- Slave Mode288
- Data Modes289
- DMA Support289
- Register Description290
- Register Summary292
- Interrupt Vector Summary292
23 Usart293
- Features293
- Overview293
- Clock Generation295
- Frame Formats298
- USART Initialization299
- Data Transmission - the USART Transmitter299
- Data Reception - the USART Receiver300
- Asynchronous Data Reception301
- Fractional Baud Rate Generation304
- USART in Master SPI Mode307
- USART SPI Vs. SPI307
- Multiprocessor Communication Mode307
- IRCOM Mode of Operation308
- DMA Support308
- Register Description309
- Register Summary315
- Interrupt Vector Summary315
24 IRCOM - IR Communication Module316
- Features316
- Overview316
- Registers Description318
- Register Summary319
25 AES and des Crypto Engines320
- Features320
- Overview320
- DES Instruction320
- AES Crypto Module321
- Register Description - AES324
- Register Summary - AES327
- Interrupt Vector Summary - AES327
26 CRC - Cyclic Redundancy Check Generator328
- Features328
- Overview328
- Operation329
- CRC on Flash Memory329
- CRC on DMA Data330
- CRC Using the I/O Interface330
- Register Description331
- Register Sumary334
27 EBI - External Bus Interface335
- Features335
- Overview335
- Chip Select335
- EBI Clock337
- SRAM Configuration337
- SRAM LPC Configuration339
- SDRAM Configuration340
- Combined SRAM & SDRAM Configuration342
- I/O Pin and Pin-Out Configuration343
- Register Description - EBI346
- Register Description - EBI Chip Select351
- Register Summary - EBI355
- Register Summary - EBI Chip Select355
28 ADC - Analog-To-Digital Converter356
- Features356
- Overview356
- Input Sources357
- ADC Channels360
- Voltage Reference Selection361
- Conversion Result361
- Compare Function363
- Starting a Conversion363
- ADC Clock and Conversion Timing363
- ADC Input Model367
- DMA Transfer368
- Interrupts and Events368
- Calibration368
- Channel Priority368
- Synchronous Sampling369
- Register Description - ADC370
- Register Description - ADC Channel377
- Register Summary - ADC384
- Register Summary - ADC Channel384
- Interrupt Vector Summary385
29 DAC - Digital to Analog Converter386
- Features386
- Overview386
- Voltage Reference Selection387
- Starting a Conversion387
- Output and Output Channels387
- DAC Output Model387
- DAC Clock388
- Low Power Mode388
- Calibration388
- Register Description390
- Register Summary397
30 AC - Analog Comparator398
- Features398
- Overview398
- Input Sources399
- Signal Compare399
- Interrupts and Events399
- Window Mode400
- Input Hysteresis400
- Propagation Delay Vs. Power Consumption400
- Register Description401
- Register Summary407
- Interrupt Vector Summary407
31 IEEE 1149.1 JTAG Boundary Scan Interface408
- Features408
- Overview408
- TAP - Test Access Port408
- JTAG Instructions410
- Boundary Scan Chain412
- Data Registers413
32 Program and Debug Interface415
- Features415
- Overview415
- PDI Physical416
- JTAG Physical420
- PDI Controller423
- Register Description - PDI Instruction and Addressing Registers427
- Register Description - PDI Control and Status Registers429
- Register Summary430
33 Memory Programming431
- Features431
- Overview431
- NVM Controller432
- NVM Commands432
- NVM Controller Busy Status432
- Flash and EEPROM Page Buffers433
- Flash and EEPROM Programming Sequences434
- Protection of NVM435
- Preventing NVM Corruption435
- CRC Functionality435
- Self-Programming and Boot Loader Support435
- External Programming446
- Register Description452
- Register Summary452
34 Peripheral Module Address Map453
35 Instruction Set Summary456
36 Appendix A: EBI Timing Diagrams461
- SRAM 3-Port ALE1 CS461
- SRAM 3-Port ALE12 CS463
- SRAM 4-Port ALE2 CS466
- SRAM 4- Port NOALE CS468
- LPC 2- Port ALE12 CS469
- LPC 3- Port ALE1 CS471
- LPC 2- Port ALE1 CS472
- SRAM 3- Port ALE1 no CS473
- SRAM 4- Port NOALE no CS475
- LPC 2- Port ALE12 no CS476
- SDRAM Init478
- SDRAM 8-Bit Write479
- SDRAM 8-Bit Read483
- SDRAM 4-Bit Write487
- SDRAM 4-Bit Read491
- SRAM Refresh494
37 Datasheet Revision History498

Atmel AVR XMEGA AU series User Manual

Table of Contents

Questions and Answers:

Atmel AVR XMEGA AU series Specifications

Related product manuals

Brand	Atmel
Model	AVR XMEGA AU series
Category	Microcontrollers
Language	English