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8331B–AVR–03/12
Atmel AVR XMEGA AU
5.12 Interrupts
The DMA controller can generate interrupts when an error is detected on a DMA channel or
when a transaction is complete for a DMA channel. Each DMA channel has a separate interrupt
vector, and there are different interrupt flags for error and transaction complete.
If repeat is not enabled, the transaction complete flag is set at the end of the block transfer. If
unlimited repeat is enabled, the transaction complete flag is also set at the end of each block
transfer.
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