Atmel AVR XMEGA AU series User Manual

351
8331B–AVR–03/12
Atmel AVR XMEGA AU
• Bit 2:0 – ROWCOLDLY[2:0]: SDRAM Row to Column Delay
This field defines the delay between an Active command and a Read/Write command as a num-
ber of Clk
PER2
cycles, according to Table 27-20 on page 351.
27.11 Register Description – EBI Chip Select
27.11.1 CTRLA – Control register A
• Bit 7 – Reserved
This bit is unused and reserved for future use.
• Bit 6:2 – ASIZE[4:0]: Address Size
These bits select the address size for the Chip Select. This is the size of the block above the
base address.
Table 27-19. SDRAM exit self-refresh delay settings.
ESRDLY[2:0] Group Configuration Description
000 0CLK Zero Clk
PER2
cycles delay
001 1CLK One Clk
PER2
cycles delay
010 2CLK Two Clk
PER2
cycles delay
011 3CLK Three Clk
PER2
cycles delay
100 4CLK Four Clk
PER2
cycles delay
101 5CLK Five Clk
PER2
cycles delay
110 6CLK Six Clk
PER2
cycles delay
111 7CLK Seven Clk
PER2
cycles delay
Table 27-20. SDRAM row column delay settings
ROWCOLDLY[2:0] Group Configuration Description
000 0CLK Zero Clk
PER2
cycles delay
001 1CLK One Clk
PER2
cycles delay
010 2CLK Two Clk
PER2
cycles delay
011 3CLK Three Clk
PER2
cycles delay
100 4CLK Four Clk
PER2
cycles delay
101 5CLK Five Clk
PER2
cycles delay
110 6CLK Six Clk
PER2
cycles delay
111 7CLK seven Clk
PER2
cycles delay
Bit 7654 3 2 10
+0x00
– ASIZE[4:0] MODE[1:0] CTRLA
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value0000 0 0 00

Atmel AVR XMEGA AU series Specifications

General

Brand	Atmel
Model	AVR XMEGA AU series
Category	Microcontrollers
Language	English