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8331B–AVR–03/12
Atmel AVR XMEGA AU
4.10.1 Bus Priority
When several masters request access to the same bus, the bus priority is in the following order
(from higher to lower priority):
1. Bus Master with ongoing access.
2. Bus Master with ongoing burst.
a. Alternating DMA controller read and DMA controller write when they access the
same data memory section.
3. Bus Master requesting burst access.
a. CPU has priority.
4. Bus Master requesting bus access.
a. CPU has priority.
4.11 Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes
one cycle, and read from SRAM takes two cycles. For burst read (DMA), new data are available
every cycle. EEPROM page load (write) takes one cycle, and three cycles are required for read.
For burst read, new data are available every second cycle. External memory has multi-cycle
read and write. The number of cycles depends on the type of memory and configuration of the
external bus interface. Refer to the instruction summary for more details on instructions and
instruction timing.
4.12 Device ID and Revision
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the
device and the device type. A separate register contains the revision number of the device.
4.13 JTAG Disable
It is possible to disable the JTAG interface from the application software. This will prevent all
external JTAG access to the device until the next device reset or until JTAG is enabled again
from the application software. As long as JTAG is disabled, the I/O pins required for JTAG can
be used as normal I/O pins.
4.14 I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this,
it is possible to lock the I/O register related to the clock system, the event system and the
advanced waveform extensions. As long as the lock is enabled, all related I/O registers are
locked and they can not be written from the application software. The lock registers themselves
are protected by the configuration change protection mechanism. For details refer to ”Configura-
tion Change Protection” on page 13.
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