343
8331B–AVR–03/12
Atmel AVR XMEGA AU
Figure 27-11. Combined SRAM and SDRAM connection
27.9 I/O Pin and Pin-out Configuration
When the EBI is enabled, it will override the direction and/or value of the I/O pins where the EBI
data lines are placed. The EBI will also override the value, but not the direction, of the I/O pins
where the EBI address and control lines are placed. These I/O pins must be configured to output
when the EBI is used. I/O pins for unused EBI address and control lines can be used as normal
I/O pins or for other alternate functions on the pins.
For control signals that are active-low, the pin output value should be set to one (high). For con-
trol signals that are active-high, the pin output value should be set to zero (low). Address lines
do not require specific pin output value configuration. The chip select lines should have pull-up
resistors to ensure that they are kept high during power on and reset. If a chip select line is
active-high, a pull-down resistor should be used instead of a pull-up.
For more details on I/O pin configuration, refer to ”I/O Ports” on page 139.
The tables below summaries the actual port pin-out for the various SRAM and SDRAM configu-
rations, and shows required pins and pin usage. Refer to the device datasheet to see which
actual I/O ports are used as EBI PORT0-3 for a specific AVR XMEGA device.
EBI
SDRAM
SRAM
WE
CAS/RE
RAS/ALE1
DQM
CLK
CKE
BA[1:0]
CS[3:0]
D[7:0]
A[7:0]/A[15:8]
WE
CAS
RAS
DQM
CLK
CKE
CS
BA[1:0]
A[7:0]
D[7:0]
D
Q
G
A[11:8]/A[19:16]
A[11:8]
A[7:0]
A[15:8]
D[7:0]
WE
CS
RE
A[19:16]
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