384
8331B–AVR–03/12
Atmel AVR XMEGA AU
28.18 Register Summary – ADC
This is the register summary when the ADC is configured to give standard 12-bit results. The register summaries for 8-bit
and 12-bit left adjusted will be similar, but with some changes in the result registers, CHnRESH and CHnRESL.
28.19 Register Summary – ADC Channel
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRLA DMASEL[1:0] CH[3:0]START FLUSH ENABLE 370
+0x01 CTRLB IMPMODE CURRLIMIT[1:0] CONVMODE FREERUN RESOLUTION[1:0] –370
+0x02 REFCTRL – REFSEL[2:0] – – BANDGAP TEMPREF 372
+0x03 EVCTRL SWEEP[1:0] EVSEL[2:0] EVACT[2:0] 372
+0x04 PRESCALER – – – – – PRESCALER[2:0] 374
+0x05 Reserved – – – – – – – –
+0x06 INTFLAGS – – – – CH[3:0]IF 374
+0x07 TEMP TEMP[7:0] 375
+0x08 Reserved – – – – – – – –
+0x09 Reserved – – – – – – – –
+0x0A Reserved – – – – – – – –
+0x0B Reserved – – – – – – – –
+0x0C CALL CAL[7:0] 375
+0x0D CALH – – – –CAL[11:8]
+0x0E Reserved
– – – – – – – –
+0x0F Reserved
– – – – – – – –
+0x10 CH0RESL CH0RES[7:0] 376
+0x11 CH0RESH CH0RES[15:8] 376
+0x12 CH1RESL CH1RES[7:0] 376
+0x13 CH1RESH CH1RES[15:8] 376
+0x14 CH2RESL CH2RES[7:0] 376
+0x15 CH2RESH CH2RES[15:8] 376
+0x16 CH3RESL CH3RES[7:0] 376
+0x17 CH3RESH CH3RES[15:8] 376
+0x18 CMPL CMP[7:0] 377
+0x19 CMPH CMP[15:8] 377
+0x1A Reserved – – – – – – – –
+0x1B Reserved – – – – – – – –
+0x1C Reserved – – – – – – – –
+0x1D Reserved – – – – – – – –
+0x1E Reserved – – – – – – – –
+0x1F Reserved – – – – – – – –
+0x20 CH0 Offset – – – – – – – –
+0x28 CH1 Offset – – – – – – – –
+0x30 CH2 Offset – – – – – – – –
+0x38 CH3 Offset – – – – – – – –
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
+0x00 CTRL START – – GAIN[2:0] INPUTMODE[1:0] 377
+0x01 MUXCTRL – MUXPOS[3:0] MUXNEG[2:0] 378
+0x02 INTCTRL
– – – – INTMODE[1:0] INTLVL[1:0] 381
+0x03 INTFLAGS
– – – – – – –IF381
+0x04 RESL RES[7:0] 382
+0x05 RESH RES[15:8] 381
+0x06 SCAN OFFSET COUNT 381
+0x07 Reserved
– – – – – – – –
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