374
8331B–AVR–03/12
Atmel AVR XMEGA AU
28.16.5 PRESCALER – Clock Prescaler register
• Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 2:0 – PRESCALER[2:0]: Prescaler Configuration
These bits define the ADC clock relative to the peripheral clock according to Table 28-9 on page
374.
28.16.6 INTFLAGS – Interrupt Flag register
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
101 SWEEP One sweep of all ADC channels defined by SWEEP on
incoming event channel with the lowest number defined by
EVSEL
110 SYNCSWEEP One sweep of all active ADC channels defined by SWEEP on
incoming event channel with the lowest number defined by
EVSE. In addition the ADC is flushed and restarted for
accurate timing
111 Reserved
Table 28-8. ADC event mode select.
Bit 76543 2 1 0
+0x04 – – – – – PRESCALER[2:0] PRESCALER
Read/Write R R R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 28-9. ADC prescaler settings.
PRESCALER[2:0] Group Configuration Peripheral Clock Division Factor
000 DIV4 4
001 DIV8 8
010 DIV16 16
011 DIV32 32
100 DIV64 64
101 DIV128 128
110 DIV256 256
111 DIV512 512
Bit 76543210
+0x06 – – – – CH[3:0]IF INTFLAGS
Read/Write R R R R R/W R/W R/W R/W
Initial Value00000000
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