373
8331B–AVR–03/12
Atmel AVR XMEGA AU
• Bit 5:3 – EVSEL[2:0]: Event Channel Input Select
These bits select which event channel will trigger which ADC channel. Each setting defines a
group of event channels, where the event channel with the lowest number will trigger ADC chan-
nel 0, the next event channel will trigger ADC channel 1, and so on. See Table 28-7 on page
373.
• Bit 2:0 – EVACT[2:0]: Event Mode
These bits select and limit how many of the selected event input channel are used, and also fur-
ther limit the ADC channels triggers. They also define more special event triggers as defined in
Table 28-7 on page 373.
Table 28-6. ADC channel select.
SWEEP[1:0] Group Configuration Active ADC Channels for Channel Sweep
00 0 Only ADC channel 0
01 01 ADC channels 0 and 1
10 012 ADC channels 0, 1, and 2
11 0123 ADC channels 0, 1, 2, and 3
Table 28-7. ADC event channel select.
EVSEL[2:0] Group Configuration Selected Event Lines
000 0123 Event channel 0, 1, 2, and 3 as selected inputs
001 1234 Event channel 1, 2, 3, and 4 as selected inputs
010 2345 Event channel 2, 3, 4, and 5 as selected inputs
011 3456 Event channel 3, 4, 5, and 6 as selected inputs
100 4567 Event channel 4, 5, 6, and 7 as selected inputs
101 567 Event channel 5, 6, and 7 as selected inputs
110 67 Event channel 6and7 as selected inputs
111 7 Event channel 7 as selected input
Table 28-8. ADC event mode select.
EVACT[2:0] Group Configuration Event Input Operation Mode
000 NONE No event inputs
001 CH0 Event channel with the lowest number defined by EVSEL
triggers conversion on ADC channel 0
010 CH01 Event channels with the two lowest numbers defined by
EVSEL trigger conversions on ADC channels 0 and 1,
respectively
011 CH012 Event channels with the three lowest numbers defined by
EVSEL trigger conversions on ADC channels 0, 1, and 2,
respectively
100 CH0123 Event channels defined by EVSEL trigger conversion on ADC
channels 0, 1, 2, and 3, respectively
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