229
8331B–AVR–03/12
Atmel AVR XMEGA AU
19.3 Register Descriptions
19.3.1 CTRL – Control register
• Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 – ENABLE: Enable
Setting this bit enables the RTC32. The synchronization time between the RTC32 and the sys-
tem clock domains is one half RTC32 clock cycle from writing the register until this has an effect
in the RTC32 clock domain; i.e., until the RTC32 starts.
For the RTC32 to start running, the PER register must also be set to a value different fromzero.
19.3.2 SYNCCTRL – Synchronisation Control/Status register
• Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4 – SYNCCNT: Enable Synchronization of the CNT Register
Setting this bit will start synchronization of the CNT register from the RTC32 clock to the system
clock domain. The bit is automatically cleared when synchronization is done.
• Bit 3:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 – SYNCBUSY: Synchronization Busy Flag
This flag is set when the CTRL or CNT register is busy synchronizing from the system clock to
the RTC32 clock domain. The CTRL register synchronization is triggered when it is written. The
CNT register is synchronized when the most-significant byte of the register is written.
Bit 76543210
+0x00
– – – – – – – ENABLE CTRL
Read/Write RRRRRRRR/W
Initial Value00000000
Bit 765 4 321 0
+0x01
– – – SYNCCNT – – – SYNCBUSY SYNCCTRL
Read/Write R R R R/W R R R R/W
Initial Value 0 0 0 0 0 0 0 0
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