390
8331B–AVR–03/12
Atmel AVR XMEGA AU
29.10 Register Description
29.10.1 CTRLA – Control Register A
• Bit 7:5 – Reserved
These bite are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4 – IDOEN: Internal Output Enable
Setting this bit will enable the internal DAC channel 0 output to be used by the Analog Compara-
tor and ADC. This will then also disable the output pin for DAC Channel 0.
• Bit 3 – CH1EN: Channel 1 Output Enable
Setting this bit will make channel 1 available on the output pin.
• Bit 2 – CH0EN: Channel 0 Output Enable
Setting this bit will make channel 0 available on the output pin unless IDOEN is set to 1.
• Bit 1 – LPMODE: Low Power Mode
Setting this bit enables the DAC low-power mode. The DAC is turned off between each conver-
sion to save current. Conversion time will be doubled when new conversions are started in this
mode.
• Bit 0 – ENABLE: Enable
This bit enables the entire DAC.
29.10.2 CTRLB – Control Register B
• Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 6:5 – CHSEL[1:0]: Channel Selection
These bits control which DAC channels are enabled and operating. Table 29-1 shows the avail-
able selections.
Bit 76543210
+0x00 – – – IDOEN CH1EN CH0EN LPMODE ENABLE CTRLA
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
+0x01 – CHSEL[1:0] – – – CH1TRIG CH0TRIG CTRLB
Read/Write R R/W R/W R R R R/W R/W
Initial Value00000000
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