342
8331B–AVR–03/12
Atmel AVR XMEGA AU
27.7.4 Timing
The Clock Enable (CKE) signal is required for SDRAM when the EBI is clocked at 2x the CPU
clock speed.
27.7.5 Initialization
Configuring Chip Select 3 to SDRAM will enable the initialization of the SDRAM. The Load Mode
Register command is automatically issued at the end of the initialization. For correct information
to be loaded to the SDRAM, one of the following must be done:
– 1. Configure the SDRAM control registers before enabling chip select 3 to SDRAM
– 2. Issue a Load Mode Register command, and perform a dummy access after the
SDRAM is initialized
The SDRAM initialization is not interruptible by other EBI accesses.
27.7.6 Refresh
The EBI will automatically handle the SDRAM refresh as long as the refresh period is config-
ured. On average will one refresh command be issues at the interval given by the SDRAM
Refresh Period Register. The EBI can collect up to four refresh commands in case the interface
is busy on another chip select or in the middle of a read/write at the time a refresh should have
been performed.
27.8 Combined SRAM & SDRAM Configuration
Combined SRAM and SDRAM configuration enables the EBI to have both SDRAM and SRAM
connected at the same time. This is available only when using a four-port EBI interface. Figure
27-11 on page 343 shows the configuration, with all interface signals.
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