281
8331B–AVR–03/12
Atmel AVR XMEGA AU
•Bit 0 – SMEN: Smart Mode Enable
This bit enables smart mode. When Smart mode is enabled, the acknowledge action, as set by
the ACKACT bit in the CTRLB register, is sent immediately after reading the DATA register.
21.10.2 CTRLB
– Control register B
• Bit 7:3
– Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
•Bit 2
– ACKACT: Acknowledge Action
This bit defines the slave's acknowledge behavior after an address or data byte is received from
the master. The acknowledge action is executed when a command is written to the CMD bits. If
the SMEN bit in the CTRLA register is set, the acknowledge action is performed when the DATA
register is read.
Table 21-7 lists the acknowledge actions.
• Bit 1:0
– CMD[1:0]: Command
Writing these bits trigger the slave operation as defined by Table 21-8. The CMD bits are strobe
bits and always read as zero. The operation is dependent on the slave interrupt flags, DIF and
APIF. The acknowledge action is only executed when the slave receives data bytes or address
byte from the master.
Bit 76543210
+0x01 – – – – – ACKACT CMD[1:0] CTRLB
Read/Write R R R R R R/W R/W R/W
Initial Value00000000
Table 21-7. TWI slave acknowledge actions.
ACKACT Action
0 Send ACK
1 Send NACK
Table 21-8. TWI slave command.
CMD[1:0]
Group
Configuration DIR Operation
00 NOACT X No action
01 X Reserved
10 COMPLETE
Used to complete transaction
0
Execute acknowledge action succeeded by waiting
for any START (S/Sr) condition
1 Wait for any START (S/Sr) condition
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