283
8331B–AVR–03/12
Atmel AVR XMEGA AU
•Bit 4 – RXACK: Received Acknowledge
This flag contains the most recently received acknowledge bit from the master. This is a read-
only flag. When read as zero, the most recent acknowledge bit from the maser was ACK, and
when read as one, the most recent acknowledge bit was NACK.
•Bit 3
– COLL: Collision
This flag is set when a slave has not been able to transfer a high data bit or a NACK bit. If a col-
lision is detected, the slave will commence its normal operation, disable data, and acknowledge
output, and no low values will be shifted out onto the SDA line. Writing a one to this bit location
will clear COLL.
The flag is also cleared automatically when a START or repeated START condition is detected.
•Bit 2
– BUSERR: TWI Slave Bus Error
This flag is set when an illegal bus condition occurs during a transfer. An illegal bus condition
occurs if a repeated START or a STOP condition is detected,and the number of bits from the
previous START condition is not a multiple of nine. Writing a one to this bit location will clear
BUSERR.
For bus errors to be detected, the bus state logic must be enabled. This is done by enabling the
TWI master.
•Bit 1
– DIR: Read/Write Direction
The R/W direction (DIR) flag reflects the direction bit from the last address packet received from
a master. When this bit is read as one, a master read operation is in progress. When read as
zero, a master write operation is in progress.
•Bit 0
– AP: Slave Address or Stop
This flag indicates whether a valid address or a STOP condition caused the last setting of APIF
in the STATUS register.
21.10.4 ADDR
– Address register
The TWI slave address register should be loaded with the 7-bit slave address (in the seven most
significant bits of ADDR) to which the TWI will respond. The lsb of ADDR is used to enable rec-
ognition of the general call address (0x00).
• Bit 7:1
– ADDR[7:1]: TWI Slave Address
SThis register contains the TWI slave address used by the slave address match logic to deter-
mine if a master has addressed the slave. The seven most-significant bits (ADDR[7:1])
represent the slave address.
Table 21-9. TWI slave address or stop.
AP Description
0 A STOP condition generated the interrupt on APIF
1 Address detection generated the interrupt on APIF
Bit 76543210
+0x03 ADDR[7:1] ADDR[0] ADDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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