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8331B–AVR–03/12
Atmel AVR XMEGA AU
•Bit 1 – QCEN: Quick Command Enable
When quick command is enabled, the corresponding interrupt flag is set immediately after the
slave acknowledges the address (read or write interrupt). At this point, software can issue either
a STOP or a repeated START condition.
•Bit 0
– SMEN: Smart Mode Enable
Setting this bit enables smart mode. When smart mode is enabled, the acknowledge action, as
set by the ACKACT bit in the CTRLC register, is sent immediately after reading the DATA
register.
21.9.3 CTRLC – Control register C
• Bits 7:3
– Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
•Bit 2
– ACKACT: Acknowledge Action
This bit defines the master's acknowledge behavior in master read mode. The acknowledge
action is executed when a command is written to the CMD bits. If SMEN in the CTRLB register is
set, the acknowledge action is performed when the DATA register is read.
Table 21-4 lists the acknowledge actions.
• Bit 1:0
– CMD[1:0]: Command
Writing the command (CMD) bits triggers a master operation as defined by Table 21-5. The
CMD bits are strobe bits, and always read as zero. The acknowledge action is only valid in mas-
ter read mode (R). In master write mode (W
), a command will only result in a repeated START or
Table 21-3. TWI master inactive bus timeout settings.
TIMEOUT[1:0] Group Configuration Description
00 DISABLED Disabled, normally used for I
2
C
01 50US 50µs, normally used for SMBus at 100kHz
10 100US 100µs
11 200US 200µs
Bit 76543210
+0x02 – – – – – ACKACT CMD[1:0] CTRLC
Read/WriteRRRRRR/WR/WR/W
Initial Value00000000
Table 21-4. ACKACT bit description.
ACKACT Action
0 Send ACK
1 Send NACK
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