Atmel AVR XMEGA AU series User Manual

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8331B–AVR–03/12
Atmel AVR XMEGA AU
18.3.2 STATUS – Status register
• Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 – SYNCBUSY: Synchronization Busy Flag
This flag is set when the CNT, CTRL, PER, or COMP register is busy synchronizing between the
RTC clock and system clock domains. THis flag is automatically cleared when the synchronisa-
tion is complete
18.3.3 INTCTRL – Interrupt Control register
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2 – COMPINTLVL[1:0]: Compare Match Interrupt Enable
These bits enable the RTC compare match interrupt and select the interrupt level, as described
in ”Interrupts and Programmable Multilevel Interrupt Controller” on page 134. The enabled inter-
rupt will trigger when COMPIF in the INTFLAGS register is set.
• Bit 1:0 – OVFINTLVL[1:0]: Overflow Interrupt Enable
These bits enable the RTC overflow interrupt and select the interrupt level, as described in
”Interrupts and Programmable Multilevel Interrupt Controller” on page 134. The enabled interrupt
will trigger when OVFIF in the INTFLAGS register is set.
Bit 7654321 0
+0x01 – – – – – – –SYNCBUSYSTATUS
Read/WriteRRRRRRR R
Initial Value0000000 0
Bit 76543210
+0x02 – – – – COMPINTLVL[1:0] OVFINTLVL[1:0] INTCTRL
Read/Write R R R R R/W R/W R/W R/W
Initial Value00000000

Atmel AVR XMEGA AU series Specifications

General

Brand	Atmel
Model	AVR XMEGA AU series
Category	Microcontrollers
Language	English