291
8331B–AVR–03/12
Atmel AVR XMEGA AU
22.7.2 INTCTRL – Interrupt Control register
• Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1:0 – INTLVL[1:0]: Interrupt Level
These bits enable the SPI interrupt and select the interrupt level, as described in ”Interrupts and
Programmable Multilevel Interrupt Controller” on page 134. The enabled interrupt will be trig-
gered when IF in the STATUS register is set.
22.7.3 STATUS – Status register
• Bit 7 – IF: Interrupt Flag
This flag is set when a serial transfer is complete and one byte is completely shifted in/out of the
DATA register. If SS
is configured as input and is driven low when the SPI is in master mode,
this will also set this flag. IF is cleared by hardware when executing the corresponding interrupt
vector. Alternatively, the IF flag can be cleared by first reading the STATUS register when IF is
set, and then accessing the DATA register.
Table 22-3. Relationship between SCK and the peripheral clock (Clk
PER
) frequency.
CLK2X PRESCALER[1:0] SCK Frequency
0 00 Clk
PER
/4
0 01 Clk
PER
/16
0 10 Clk
PER
/64
0 11 Clk
PER
/128
1 00 Clk
PER
/2
1 01 Clk
PER
/8
1 10 Clk
PER
/32
1 11 Clk
PER
/64
Bit 76543210
+0x01 – – – – – – INTLVL[1:0] INTCTRL
Read/WriteRRRRRRR/WR/W
Initial Value00000000
Bit 76543210
+0x02 IF WRCOL
– – – – – –STATUS
Read/WriteRRRRRRRR
Initial Value 0 0 0 0 0 0 0 0
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