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AVR XMEGA AU series
Atmel AVR XMEGA AU series User Manual
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305
8331B–AVR–03/12
Atmel AVR XMEGA AU
Figure 23-9.
F
ractional baud rate ex
ample.
BSEL=0
BSCALE=0
f
BAUD
=f
PER
/8
clk
BAUD8
clk
BAUD8
BSEL=3
BSCALE=-6
f
BAUD
=f
PER
/8.375
clk
BAUD8
BSEL=3
BSCALE=-4
f
BAUD
=f
PER
/9.5
Extra clock cycle added
304
306
Table of Contents
1 About the Manual
2
Reading the Manual
2
Resources
2
Recommended Reading
2
2 Overview
3
3 Avr Cpu
7
Features
7
Overview
7
Architectural Overview
7
ALU - Arithmetic Logic Unit
8
Program Flow
9
Instruction Execution Timing
9
Status Register
10
Stack and Stack Pointer
10
Register File
11
RAMP and Extended Indirect Registers
12
Accessing 16-Bit Registers
13
Configuration Change Protection
13
Fuse Lock
14
Register Descriptions
15
Register Summary
19
4 Memories
20
Features
20
Overview
20
Flash Program Memory
21
Fuses and Lockbits
22
Data Memory
23
Internal SRAM
23
Eeprom
23
I/O Memory
24
External Memory
24
Data Memory and Bus Arbitration
24
Memory Timing
25
Device ID and Revision
25
JTAG Disable
25
I/O Memory Protection
25
Register Description - NVM Controller
26
Register Descriptions - Fuses and Lock Bits
31
Register Description - Production Signature Row
37
Register Description - General Purpose I/O Memory
46
Register Description - External Memory
46
Register Descriptions - MCU Control
47
Register Summary - NVM Controller
51
Register Summary - Fuses and Lockits
51
Register Summary - Production Signature Row
52
Register Summary - General Purpose I/O Registers
53
Register Summary - MCU Control
53
Interrupt Vector Summary - NVM Controller
53
5 DMAC - Direct Memory Access Controller
54
Features
54
Overview
54
DMA Transaction
55
Transfer Triggers
56
Addressing
56
Priority between Channels
56
Double Buffering
57
Transfer Buffers
57
Error Detection
57
Software Reset
57
Protection
57
Interrupts
58
Register Description - DMA Controller
59
Register Description - DMA Channel
61
Register Summary - DMA Controller
70
Register Summary - DMA Channel
70
DMA Interrupt Vector Summary
70
6 Event System
71
Features
71
Overview
71
Events
72
Event Routing Network
74
Event Timing
76
Filtering
76
Quadrature Decoder
76
Register Description
78
Register Summary
82
7 System Clock and Clock Options
83
Features
83
Overview
83
Clock Distribution
85
Clock Sources
85
System Clock Selection and Prescalers
87
PLL with 1X-31X Multiplication Factor
88
DFLL 2Mhz and DFLL 32Mhz
89
PLL and External Clock Source Failure Monitor
90
Register Description - Clock
92
Register Description - Oscillator
96
Register Description - DFLL32M/DFLL2M
101
Register Summary - Clock
104
Register Summary - Oscillator
104
Register Summary - DFLL32M/DFLL2M
104
Oscillator Failure Interrupt Vector Summary
104
8 Power Management and Sleep Modes
105
Features
105
Overview
105
Sleep Modes
105
Power Reduction Registers
107
Minimizing Power Consumption
107
Register Description - Sleep
109
Register Description - Power Reduction
109
Register Summary - Sleep
112
Register Summary - Power Reduction
112
9 Reset System
113
Features
113
Overview
113
Reset Sequence
114
Reset Sources
115
Register Description
119
Register Summary
120
10 Battery Backup System
121
Features
121
Overview
121
Battery Backup System
122
Configuration
123
Operation
123
Register Description
125
Register Summary
127
11 WDT - Watchdog Timer
128
Features
128
Overview
128
Normal Mode Operation
128
Window Mode Operation
129
Watchdog Timer Clock
129
Configuration Protection and Lock
130
Registers Description
130
Register Summary
133
12 Interrupts and Programmable Multilevel Interrupt Controller
134
Features
134
Overview
134
Operation
134
Interrupts
135
Interrupt Level
138
Interrupt Priority
138
Interrupt Vector Locations
140
Register Description
141
Register Summary
142
13 O Ports
143
Features
143
Overview
143
I/O Pin Use and Configuration
144
Reading the Pin Value
147
Input Sense Configuration
148
Port Interrupt
149
Port Event
150
Alternate Port Functions
150
Slew Rate Control
151
Clock and Event Output
151
Multi-Pin Configuration
152
Virtual Ports
152
Register Descriptions - Ports
153
Register Descriptions - Port Configuration
159
Register Descriptions - Virtual Port
164
Register Summary - Ports
166
Register Summary - Port Configuration
166
Register Summary - Virtual Ports
166
Interrupt Vector Summary - Ports
167
14 TC0/1 - 16-Bit Timer/Counter Type 0 and 1
168
Features
168
Overview
168
Block Diagram
170
Clock and Event Sources
171
Double Buffering
171
Counter Operation
172
Capture Channel
175
Compare Channel
177
Interrupts and Events
181
DMA Support
181
Timer/Counter Commands
181
Register Description
182
Register Summary
192
Interrupt Vector Summary
192
15 TC2 - 16-Bit Timer/Counter Type 2
193
Features
193
Overview
193
Clock Sources
194
Counter Operation
195
Compare Channel
196
Interrupts and Events
197
DMA Support
198
Timer/Counter Commands
198
Register Description
199
Register Summary
205
Interrupt Vector Summary
205
16 Awex - Advanced Waveform Extension
206
Features
206
Overview
206
Port Override
207
Dead-Time Insertion
208
Pattern Generation
209
Fault Protection
210
Register Description
212
Register Summary
216
17 Hi-Res - High-Resolution Extension
217
Features
217
Overview
217
Register Description
218
Register Summary
218
18 RTC - Real-Time Counter
219
Features
219
Overview
219
Register Descriptions
221
Register Summary
226
Interrupt Vector Summary
226
19 RTC32 - 32-Bit Real-Time Counter
227
Features
227
Overview
227
Register Descriptions
229
Register Summary
234
Interrupt Vector Summary
234
20 USB - Universal Serial Bus Interface
235
Features
235
Overview
235
Operation
237
SRAM Memory Mapping
240
Clock Generation
241
Ping-Pong Operation
242
Multipacket Transfers
243
Auto Zero Length Packet
244
Transaction Complete FIFO
244
Interrupts and Events
245
VBUS Detection
247
On-Chip Debug
247
Register Description - USB
248
Register Description - USB Endpoint
255
Register Description - Frame
260
Register Summary - USB Module
261
Register Summary - USB Endpoint
261
Register Summary - Frame
261
USB Interrupt Vector Summary
261
21 TWI - Two-Wire Interface
262
Features
262
Overview
262
General TWI Bus Concepts
263
TWI Bus State Logic
268
TWI Master Operation
269
TWI Slave Operation
271
Enabling External Driver Interface
273
Register Description - TWI
274
Register Description - TWI Master
275
Register Description - TWI Slave
280
Register Summary - TWI
286
Register Summary - TWI Master
286
Register Summary - TWI Slave
286
Interrupt Vector Summary
286
22 SPI - Serial Peripheral Interface
287
Features
287
Overview
287
Master Mode
288
Slave Mode
288
Data Modes
289
DMA Support
289
Register Description
290
Register Summary
292
Interrupt Vector Summary
292
23 Usart
293
Features
293
Overview
293
Clock Generation
295
Frame Formats
298
USART Initialization
299
Data Transmission - the USART Transmitter
299
Data Reception - the USART Receiver
300
Asynchronous Data Reception
301
Fractional Baud Rate Generation
304
USART in Master SPI Mode
307
USART SPI Vs. SPI
307
Multiprocessor Communication Mode
307
IRCOM Mode of Operation
308
DMA Support
308
Register Description
309
Register Summary
315
Interrupt Vector Summary
315
24 IRCOM - IR Communication Module
316
Features
316
Overview
316
Registers Description
318
Register Summary
319
25 AES and des Crypto Engines
320
Features
320
Overview
320
DES Instruction
320
AES Crypto Module
321
Register Description - AES
324
Register Summary - AES
327
Interrupt Vector Summary - AES
327
26 CRC - Cyclic Redundancy Check Generator
328
Features
328
Overview
328
Operation
329
CRC on Flash Memory
329
CRC on DMA Data
330
CRC Using the I/O Interface
330
Register Description
331
Register Sumary
334
27 EBI - External Bus Interface
335
Features
335
Overview
335
Chip Select
335
EBI Clock
337
SRAM Configuration
337
SRAM LPC Configuration
339
SDRAM Configuration
340
Combined SRAM & SDRAM Configuration
342
I/O Pin and Pin-Out Configuration
343
Register Description - EBI
346
Register Description - EBI Chip Select
351
Register Summary - EBI
355
Register Summary - EBI Chip Select
355
28 ADC - Analog-To-Digital Converter
356
Features
356
Overview
356
Input Sources
357
ADC Channels
360
Voltage Reference Selection
361
Conversion Result
361
Compare Function
363
Starting a Conversion
363
ADC Clock and Conversion Timing
363
ADC Input Model
367
DMA Transfer
368
Interrupts and Events
368
Calibration
368
Channel Priority
368
Synchronous Sampling
369
Register Description - ADC
370
Register Description - ADC Channel
377
Register Summary - ADC
384
Register Summary - ADC Channel
384
Interrupt Vector Summary
385
29 DAC - Digital to Analog Converter
386
Features
386
Overview
386
Voltage Reference Selection
387
Starting a Conversion
387
Output and Output Channels
387
DAC Output Model
387
DAC Clock
388
Low Power Mode
388
Calibration
388
Register Description
390
Register Summary
397
30 AC - Analog Comparator
398
Features
398
Overview
398
Input Sources
399
Signal Compare
399
Interrupts and Events
399
Window Mode
400
Input Hysteresis
400
Propagation Delay Vs. Power Consumption
400
Register Description
401
Register Summary
407
Interrupt Vector Summary
407
31 IEEE 1149.1 JTAG Boundary Scan Interface
408
Features
408
Overview
408
TAP - Test Access Port
408
JTAG Instructions
410
Boundary Scan Chain
412
Data Registers
413
32 Program and Debug Interface
415
Features
415
Overview
415
PDI Physical
416
JTAG Physical
420
PDI Controller
423
Register Description - PDI Instruction and Addressing Registers
427
Register Description - PDI Control and Status Registers
429
Register Summary
430
33 Memory Programming
431
Features
431
Overview
431
NVM Controller
432
NVM Commands
432
NVM Controller Busy Status
432
Flash and EEPROM Page Buffers
433
Flash and EEPROM Programming Sequences
434
Protection of NVM
435
Preventing NVM Corruption
435
CRC Functionality
435
Self-Programming and Boot Loader Support
435
External Programming
446
Register Description
452
Register Summary
452
34 Peripheral Module Address Map
453
35 Instruction Set Summary
456
36 Appendix A: EBI Timing Diagrams
461
SRAM 3-Port ALE1 CS
461
SRAM 3-Port ALE12 CS
463
SRAM 4-Port ALE2 CS
466
SRAM 4- Port NOALE CS
468
LPC 2- Port ALE12 CS
469
LPC 3- Port ALE1 CS
471
LPC 2- Port ALE1 CS
472
SRAM 3- Port ALE1 no CS
473
SRAM 4- Port NOALE no CS
475
LPC 2- Port ALE12 no CS
476
SDRAM Init
478
SDRAM 8-Bit Write
479
SDRAM 8-Bit Read
483
SDRAM 4-Bit Write
487
SDRAM 4-Bit Read
491
SRAM Refresh
494
37 Datasheet Revision History
498
4
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Atmel AVR XMEGA AU series Specifications
General
Brand
Atmel
Model
AVR XMEGA AU series
Category
Microcontrollers
Language
English
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