Atmel AVR XMEGA AU series - Page 508

ix
8331B–AVR–03/12
Atmel AVR XMEGA AU
25 AES and DES Crypto Engines ............................................................ 320
25.1 Features ........................................................................................................320
25.2 Overview ........................................................................................................320
25.3 DES Instruction ..............................................................................................320
25.4 AES Crypto Module .......................................................................................321
25.5 Register Description – AES ...........................................................................324
25.6 Register Summary - AES ..............................................................................327
25.7 Interrupt vector Summary - AES ....................................................................327
26 CRC – Cyclic Redundancy Check Generator .................................... 328
26.1 Features ........................................................................................................328
26.2 Overview ........................................................................................................328
26.3 Operation .......................................................................................................329
26.4 CRC on Flash memory ..................................................................................329
26.5 CRC on DMA Data ........................................................................................330
26.6 CRC using the I/O Interface ..........................................................................330
26.7 Register Description ......................................................................................331
26.8 Register Sumary ...........................................................................................334
27 EBI – External Bus Interface ............................................................... 335
27.1 Features ........................................................................................................335
27.2 Overview ........................................................................................................335
27.3 Chip Select ....................................................................................................335
27.4 EBI Clock .......................................................................................................337
27.5 SRAM Configuration ......................................................................................337
27.6 SRAM LPC Configuration ..............................................................................339
27.7 SDRAM Configuration ...................................................................................340
27.8 Combined SRAM & SDRAM Configuration ...................................................342
27.9 I/O Pin and Pin-out Configuration ..................................................................343
27.10 Register Description – EBI ............................................................................346
27.11 Register Description – EBI Chip Select .........................................................351
27.12 Register Summary - EBI ................................................................................355
27.13 Register Summary - EBI Chip Select ............................................................355
28 ADC – Analog-to-Digital Converter .................................................... 356
28.1 Features ........................................................................................................356
28.2 Overview ........................................................................................................356
28.3 Input Sources ................................................................................................357