Atmel AVR XMEGA AU series - Page 510

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8331B–AVR–03/12
Atmel AVR XMEGA AU
30.6 Window Mode ................................................................................................400
30.7 Input Hysteresis .............................................................................................400
30.8 Propagation Delay vs. Power Consumption ..................................................400
30.9 Register Description ......................................................................................401
30.10 Register Summary .........................................................................................407
30.11 Interrupt vector Summary ..............................................................................407
31 IEEE 1149.1 JTAG Boundary Scan Interface ..................................... 408
31.1 Features ........................................................................................................408
31.2 Overview ........................................................................................................408
31.3 TAP - Test Access Port .................................................................................408
31.4 JTAG Instructions ..........................................................................................410
31.5 Boundary Scan Chain ....................................................................................412
31.6 Data Registers ...............................................................................................413
32 Program and Debug Interface ............................................................. 415
32.1 Features ........................................................................................................415
32.2 Overview ........................................................................................................415
32.3 PDI Physical ..................................................................................................416
32.4 JTAG Physical ...............................................................................................420
32.5 PDI Controller ................................................................................................423
32.6 Register Description - PDI Instruction and Addressing Registers .................427
32.7 Register Description – PDI Control and Status Registers .............................429
32.8 Register Summary .........................................................................................430
33 Memory Programming ......................................................................... 431
33.1 Features ........................................................................................................431
33.2 Overview ........................................................................................................431
33.3 NVM Controller ..............................................................................................432
33.4 NVM Commands ...........................................................................................432
33.5 NVM Controller Busy Status ..........................................................................432
33.6 Flash and EEPROM Page Buffers ................................................................433
33.7 Flash and EEPROM Programming Sequences .............................................434
33.8 Protection of NVM .........................................................................................435
33.9 Preventing NVM Corruption ...........................................................................435
33.10 CRC Functionality ..........................................................................................435
33.11 Self-programming and Boot Loader Support .................................................435
33.12 External Programming ...................................................................................446