60
8331B–AVR–03/12
Atmel AVR XMEGA AU
5.13.2 INTFLAGS – Interrupt Status register
• Bit 7:4 – CHnERRIF[3:0]: Channel n Error Interrupt Flag
If an error condition is detected on DMA channel n, the CHnERRIF flag will be set. Writing a one
to this bit location will clear the flag.
• Bit 3:0 – CHnTRNFIF[3:0]: Channel n Transaction Complete Interrupt Flag
When a transaction on channel n has been completed, the CHnTRFIF flag will be set. If unlim-
ited repeat count is enabled, this flag is read as one after each block transfer. Writing a one to
this bit location will clear the flag.
5.13.3 STATUS – Status register
• Bit 7:4 – CHnBUSY[3:0]: Channel Busy
When channel n starts a DMA transaction, the CHnBUSY flag will be read as one. This flag is
automatically cleared when the DMA channel is disabled, when the channel n transaction com-
plete interrupt flag is set, or if the DMA channel n error interrupt flag is set.
• Bit 3:0 – CHnPEND[3:0]: Channel Pending
If a block transfer is pending on DMA channel n, the CHnPEND flag will be read as one. This
flag is automatically cleared when the block transfer starts or if the transfer is aborted.
5.13.4 TEMPL – Temporary register Low
• Bit 7:0 – TEMP[7:0]: Temporary register 0
This register is used when reading 16- and 24-bit registers in the DMA controller. Byte 1 of the
16/24-bit register is stored here when it is written by the CPU. Byte 1 of the 16/24-bit register is
stored when byte 0 is read by the CPU. This register can also be read and written from the user
software.
Reading and writing 16- and 24-bit registers requires special attention. For details, refer to
”Accessing 16-bit Registers” on page 13.
Bit 7654 3 2 1 0
+0x03 CH3ERRIF CH2ERRIF CH1ERRIF CH0ERRIF CH3TRNFIF CH2TRNFIF CH1TRNFIF CH0TRNFIF INTFLAGS
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x04 CH3BUSY CH2BUSY CH1BUSY CH0BUSY CH3PEND CH2PEND CH1PEND CH0PEND STATUS
Read/WriteRRRRRRRR
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x06 TEMP[7:0] TEMPL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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