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xvii

List of Tables

Table 1-1. MTX Series Features Summary................................................................1-1

Table 1-2. Default Processor Memory Map...............................................................1-5

Table 1-3. CHRP Memory Map Example..................................................................1-6

Table 1-4. Raven MPC Register Values for CHRP Memory Map.............................1-8

Table 1-5. PREP Memory Map Example...................................................................1-8

Table 1-6. Raven MPC Register Values for PREP Memory Map .............................1-9

Table 1-7. PCI CHRP Memory Map Example ........................................................1-11

Table 1-8. Raven PCI Register Values for CHRP Memory Map.............................1-11

Table 1-9. PCI PREP Memory Map.........................................................................1-12

Table 1-10. Raven PCI Register Values for PREP Memory Map............................1-12

Table 1-11. PVR Values ...........................................................................................1-13

Table 1-12. Typical DIMM SPD Information..........................................................1-15

Table 1-13. System Register Summary....................................................................1-16

Table 1-14. Strap Pins Configuration for the PC87308VUL ...................................1-24

Table 1-15. MK48T59/559 Access Registers ..........................................................1-24

Table 1-16. Module Configuration and Status Registers .........................................1-25

Table 1-17. Z8536/Z85230 Access Registers ..........................................................1-30

Table 1-18. Z8536 CIO Port Pins Assignment.........................................................1-30

Table 1-19. I2C Controller Access Registers...........................................................1-31

Table 1-20. Two Wire Serial (I2C) Bus Addresses..................................................1-32

Table 1-21. PIB DMA Channel Assignments..........................................................1-32

Table 2-1. CHRP Compliant Memory Map...............................................................2-4

Table 2-2. PPC Transfer Types ..................................................................................2-8

Table 2-3. PCI Command Codes..............................................................................2-11

Table 2-4. Address Modification for Little-Endian Transfers .................................2-16

Table 2-5. Raven PPC Register Map .......................................................................2-21

Table 2-6. Raven PCI Configuration Register Map.................................................2-37

Table 2-7. Raven PCI I/O Register Map..................................................................2-38

Table 2-8. Raven MPIC Register Map.....................................................................2-58

Table 3-1. PowerPC 60x Bus to DRAM Access Timing when Configured for

70ns Fast Page Devices..............................................................................................3-7

Table 3-2. PowerPC 60x Bus to DRAM Access Timing when Configured for

60ns Fast Page Devices..............................................................................................3-8

Table 3-3. PowerPC 60x Bus to DRAM Access Timing when Configured for

50ns EDO Devices...................................................................................................3-10

Motorola MTX series Programmer's Reference Guide

Other manuals for Motorola MTX series