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Falcon ECC Memory Controller Chip Set
3
1. Disable scrub writes by clearing the swen bit if it is set.
2. Make sure software is not using DRAM at this point, because while
rwcb is set, DRAM will not function as normal memory.
3. Set the derc and rwcb bits in the Data Control register.
4. Perform the desired read and/or write check-bit operations.
5. Clear the derc and rwcb bits in the Data Control register.
6. Perform the desired testing related to the location/locations that
have had their check-bits altered.
7. Enable scrub writes by setting the swen bit if it was set before.
derc Setting derc to one alters Falcon pair operation as follows:
1. During reads, data is presented to the PowerPC 60x data bus
uncorected from the DRAM array.
2. During single-beat writes, data is written without correcting single-
bit errors that may occur on the read portion of the read-modify-
write. Check-bits are generated for the data being written.
3. During single-beat writes, the write portion of the read-modify-
write happens regardless of whether there is a multiple-bit error
during the read portion. No correction of data is attempted. Check-
bits are generated for the data being written.
4. During refresh/scrub cycles, if swen is set, a read-write to DRAM
happens with no attempt to correct data bits. Check-bits are
generated for the data being written.
derc is useful for initializing DRAM after power-up and for testing
DRAM, but it should be cleared during normal system operation.
scien When scien is set, the rolling over of the SBE COUNT register
causes the INT_ signal pin to pulse true.
dpien When dpien is set, the logging of a 60x data parity error causes the
INT_ signal pin to pulse true.
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