IN-1
Index
Numerics
32-Bit Counter 3-56
8259 compatibility 2-50
8259 interrupts 4-5
8259 mode 2-77
A
A0-A31 3-5
access timing (DRAM) 3-7, 3-8
Access Timing (ROM) 3-11, 3-12
address modification for little endian trans-
fers 2-16
address pipelining 3-6
address transfers 3-13
Application-Specific Integrated Circuit
(ASIC) xix
architectural notes 2-78
architecture 2-48
ARTRY_ 3-14
assertion, definition xxi
asterisk (*) xxi
B
Base Module Feature Register 1-26
Base Module Status Register (BMSR) 1-27
big to little endian data swap 2-15
big-endian xxii
big-endian mode 4-11
binary number xxi
bit descriptions 3-32
bit ordering convention 3-1
block diagram 2-3
block diagram description 2-52
block diagrams 3-2
blocks A and/or B present, blocks C and D
not present 3-22
blocks A and/or B present, blocks C and/or D
present 3-23
bus interface (60x) 3-12
byte ordering xxii
byte, definition xxi
C
cache coherency 3-13
cache coherency restrictions 3-14
chip defaults 3-24
CHRP compliant memory map 2-4
CHRP memory map example 1-6
CLK FREQUENCY 3-37
clock frequency 3-37
Column Address bits 3-46
CONFIG_ADDRESS 2-45
control bit descriptions 3-32
control bit, definition xxii
conventions, manual xxi
CPU Control Register 1-23
CSR accesses 3-24
CSR architecture 3-25
CSR base address 3-25
CSR reads and writes 3-25
CSR’s readability 2-48
current task priority level 2-78
cycles originating from PCI 2-16
D
data path diagram 3-65
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