Index
IN-2 Computer Group Literature Center Web Site
I
N
D
E
X
data path for reads from the Falcon internal
CSRs 3-25
data path for writes to the Falcon internal
CSRs 3-26
data path mapping 3-66
data paths 3-64
data transfers 3-13
decimal number xxi
default PCI memory map 1-10
default processor memory map 1-5
derc 3-40
Disable Error Correction control bit 3-40
double word, definition xxii
DRAM addressing 3-61
DRAM attributes register 3-35
DRAM Base Register 3-37
DRAM connection diagram 3-5
DRAM enable bits 3-35
DRAM size control bits 3-36
DRAM speed control bits 3-34
DRAM speeds 3-7
dynamically changing I/O interrupt configu-
ration 2-77
E
ECC 3-14
ECC codes 3-62
ECC Control Register 3-38
elog 3-42
embt 3-43
endian conversion 2-14
endian issues 4-11
End-of-Interrupt Registers 2-74
EOI Register 2-77
Error Address Register 3-44
error correction 3-14
Error Correction Codes 3-62
error detection 3-14
error handling 2-16
Error Logger Register 3-41
error logging 3-18
error notification and handling 4-9, 4-10
error reporting 3-17
ERROR_ADDRESS 3-44
ERROR_SYNDROME 3-43
esbt 3-43
escb 3-42
esen 3-42
exceptions 4-8
External Register Set 3-57
external register set 3-24
external register set reads and writes 3-25
External Source Destination Registers 2-70
External Source Vector/Priority Registers
2-69
F
Falcon ECC memory controller chip set 3-1
Falcon pair used with DRAM in a system 3-3
Falcon-controlled system registers 1-16
false, definition xxii
fast refresh control bit 3-34
Feature Reporting Register 2-61
features 2-1, 3-1
Flash (See ROM/Flash) 3-18
four-beat reads/writes 3-6
functional description 1-3, 2-4, 3-6
G
General Control-Status/Feature Registers
2-23
General Purpose Registers 2-36
generating PCI configuration cycles 2-13
generating PCI interrupt acknowledge cycles
2-14
generating PCI memory and I/O cycles 2-12
generating PCI special cycles 2-14
Global Configuration Register 2-61
H
half-word, definition xxi
hexadecimal character xxi
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