http://www.motorola.com/computer/literature IN-3
I
N
D
E
X
I
I/O Base Register 2-41
In-Service Register (ISR) 2-55
Interprocessor Interrupt Dispatch Registers
2-72
interprocessor interrupts 2-76
interprocessor interrupts (IPI) 2-49
Interrupt Acknowledge Register 2-77
Interrupt Acknowledge Registers 2-73
interrupt delivery modes 2-51
Interrupt Enable Control Bits 3-40
Interrupt Enable control bits 3-40
interrupt handling 4-3
Interrupt Pending Register (IPR) 2-54
Interrupt Request Register (IRR) 2-55
interrupt router 2-55
interrupt selector (IS) 2-54
interrupt source priority 2-48
Interrupt Task Priority Registers 2-73
introduction 2-1, 2-47, 3-1, 4-1
IPI Vector/Priority Registers 2-64
ISA DMA channels 1-32, 4-8
ISA local resource bus 1-23
L
L2 cache support 3-14
L2CLM_ 3-14
Large Scale Integration (LSI) xix
little-endian xxii
little-endian mode 4-12
M
manual terminology xxi
manufacturers’ documents A-1
mcken 3-41
Memory Base Register 2-42
Memory Configuration Register (MEMCR)
1-18
memory map for 4-byte reads to the CSR
3-29
memory map for 4-byte writes to the internal
register set and test SRAM 3-29
memory map for byte reads to the CSR 3-27
memory map for byte writes to the internal
register set and test SRAM 3-28
memory maps 1-5
mien 3-41
MK48T59 access registers 1-24
module configuration and status registers
1-25
Motorola Computer Group documents A-1
MPC bus interface 2-4
MPC bus timer 2-9
MPC Error Address Register 2-30
MPC Error Attribute Register - MERAT 2-30
MPC Error Enable Register 2-26
MPC Error Status Register 2-28
MPC map decoders 2-4
MPC master 2-6
MPC registers 2-21
MPC Slave Address (0,1 and 2) Registers
2-33
MPC Slave Address (3) Register 2-33
MPC Slave Offset/Attribute (0,1 and 2) Reg-
isters 2-34
MPC Slave Offset/Attribute (3) Registers
2-35
MPC transfer types 2-8
MPC write posting 2-5
MPIC registers 2-57
MVME2600 series 1-1
MVME2600 series features summary 1-1
MVME2600 series interrupt architecture 4-3
MVME2600 series system block diagram 1-4
N
negation, definition xxi
nesting of interrupt events 2-49
NVRAM/RTC & Watchdog Timer Registers
1-24
O
operation 2-76
overall DRAM connections 3-5