viii
W83C553 PIB Registers ..................................................................................1-23
Primary and Secondary EIDE Ports ................................................................. 1-23
PC87308VUL Super I/O Strapping.................................................................. 1-24
NVRAM/RTC & Watchdog Timer Registers................................................... 1-24
Module Configuration and Status Registers..................................................... 1-25
CPU Configuration Register ..................................................................... 1-25
Base Module Feature Register .................................................................. 1-26
Base Module Status Register (BMSR)...................................................... 1-27
Extended Status Register........................................................................... 1-27
SCSI Terminator Select............................................................................. 1-28
Seven-Segment Display Register..............................................................1-29
Z85230 ESCC and Z8536 CIO Registers and Port Pins .................................. 1-29
Z8536/Z85230 Registers........................................................................... 1-29
Z8536 CIO Port Pins................................................................................. 1-30
Two Wire Serial (I2C) Bus Controller...................................................... 1-31
ISA DMA Channels ......................................................................................... 1-32
CHAPTER 2 Raven PCI Host Bridge & Multi-Processor Interrupt Controller
Introduction ...............................................................................................................2-1
Overview ............................................................................................................ 2-1
Requirements......................................................................................................2-1
Features ..............................................................................................................2-1
Block Diagram...........................................................................................................2-3
Functional Description .............................................................................................. 2-4
PPC Bus Interface ..............................................................................................2-4
PPC Map Decoders .....................................................................................2-4
PPC Write Posting.......................................................................................2-5
PPC Master..................................................................................................2-6
PPC Bus Timer............................................................................................2-9
PCI Interface.......................................................................................................2-9
PCI Map Decoders ......................................................................................2-9
PCI Configuration Space........................................................................... 2-10
PCI Write Posting .....................................................................................2-10
PCI Master ................................................................................................ 2-11
Generating PCI Memory and I/O Cycles ......................................................... 2-12
Generating PCI Configuration Cycles.............................................................. 2-13
Generating PCI Special Cycles ........................................................................2-14
Generating PCI Interrupt Acknowledge Cycles............................................... 2-14
Endian Conversion ........................................................................................... 2-14
When PPC Devices are Big-Endian..........................................................2-15
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