Motorola MTX series - Page 9

ix
When PPC Devices are Little-Endian .......................................................2-16
Cycles Originating From PCI....................................................................2-16
Error Handling..................................................................................................2-16
PCI/PPC Contention Handling .........................................................................2-18
Transaction Ordering ........................................................................................2-19
Registers...................................................................................................................2-20
PPC Registers ...................................................................................................2-21
Vendor ID/Device ID Registers ................................................................2-22
Revision ID Register .................................................................................2-23
General Control-Status/Feature Registers .................................................2-23
Prescaler Adjust Register...........................................................................2-25
PPC Error Enable Register ........................................................................2-26
PPC Error Status Register..........................................................................2-28
PPC Error Address Register ......................................................................2-30
PPC Error Attribute Register - MERAT....................................................2-30
PCI Interrupt Acknowledge Register ........................................................2-32
PPC Slave Address (0,1 and 2) Registers..................................................2-33
PPC Slave Address (3) Register................................................................2-33
PPC Slave Offset/Attribute (0,1 and 2) Registers .....................................2-34
PPC Slave Offset/Attribute (3) Registers ..................................................2-35
General Purpose Registers.........................................................................2-36
PCI Registers ....................................................................................................2-37
Vendor ID/ Device ID Registers ...............................................................2-38
PCI Command/ Status Registers................................................................2-39
Revision ID/ Class Code Registers............................................................2-40
Header Type Register................................................................................2-41
I/O Base Register.......................................................................................2-41
Memory Base Register ..............................................................................2-42
PCI Slave Address (0,1,2 and 3) Registers................................................2-43
PCI Slave Attribute/ Offset (0,1,2 and 3) Registers ..................................2-44
CONFIG_ADDRESS................................................................................2-45
PCI I/O CONFIG_ADDRESS Register ....................................................2-45
PCI I/O CONFIG_DATA Register ...........................................................2-47
Raven Interrupt Controller Implementation.............................................................2-47
Introduction.......................................................................................................2-47
The Raven Interrupt Controller (Raven MPIC) Features ..........................2-47
Architecture ...............................................................................................2-48
CSR’s Readability .....................................................................................2-48
Interrupt Source Priority............................................................................2-48
Processor’s Current Task Priority..............................................................2-49
Nesting of Interrupt Events........................................................................2-49