x
Spurious Vector Generation...................................................................... 2-49
Interprocessor Interrupts (IPI)................................................................... 2-49
8259 Compatibility.................................................................................... 2-50
Raven-Detected Errors.............................................................................. 2-50
Timers ....................................................................................................... 2-50
Interrupt Delivery Modes.......................................................................... 2-51
Block Diagram Description..............................................................................2-52
Program Visible Registers......................................................................... 2-54
Interrupt Pending Register (IPR) ..............................................................2-54
Interrupt Selector (IS) ............................................................................... 2-54
Interrupt Request Register (IRR) .............................................................. 2-55
In-Service Register (ISR)..........................................................................2-55
Interrupt Router......................................................................................... 2-55
MPIC Registers ................................................................................................2-57
Raven MPIC Registers..............................................................................2-57
Feature Reporting Register ....................................................................... 2-61
Global Configuration Register .................................................................. 2-61
Vendor Identification Register..................................................................2-63
Processor Init Register .............................................................................. 2-63
IPI Vector/Priority Registers..................................................................... 2-64
Spurious Vector Register ..........................................................................2-65
Timer Frequency Register......................................................................... 2-65
Timer Current Count Registers ................................................................. 2-66
Timer Basecount Registers .......................................................................2-66
Timer Vector/Priority Registers................................................................ 2-67
Timer Destination Registers...................................................................... 2-68
External Source Vector/Priority Registers................................................ 2-69
External Source Destination Registers...................................................... 2-70
Raven-Detected Errors Vector/Priority Register ...................................... 2-71
Raven-Detected Errors Destination Register ............................................ 2-72
Interprocessor Interrupt Dispatch Registers.............................................. 2-72
Interrupt Task Priority Registers...............................................................2-73
Interrupt Acknowledge Registers.............................................................. 2-73
End-of-Interrupt Registers ........................................................................2-74
Programming Notes.......................................................................................... 2-74
External Interrupt Service ......................................................................... 2-74
Reset State................................................................................................. 2-76
Operation.......................................................................................................... 2-76
Interprocessor Interrupts ........................................................................... 2-76
Dynamically Changing I/O Interrupt Configuration................................. 2-77
EOI Register..............................................................................................2-77
Interrupt Acknowledge Register ............................................................... 2-77