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8259 Mode.................................................................................................2-77
Current Task Priority Level.......................................................................2-78
Architectural Notes...........................................................................................2-78
CHAPTER 3 Falcon ECC Memory Controller Chip Set
Introduction................................................................................................................3-1
Overview.............................................................................................................3-1
Bit Ordering Convention ....................................................................................3-1
Features...............................................................................................................3-1
Block Diagrams .........................................................................................................3-2
Functional Description...............................................................................................3-6
Performance........................................................................................................3-6
Four-beat Reads/Writes...............................................................................3-6
Single-beat Reads/Writes ............................................................................3-7
DRAM Speeds.............................................................................................3-7
ROM/Flash Speeds....................................................................................3-11
PowerPC 60x Bus Interface..............................................................................3-12
Responding to Address Transfers..............................................................3-13
Completing Data Transfers........................................................................3-13
Data Parity.................................................................................................3-13
Cache Coherency.......................................................................................3-14
Cache Coherency Restrictions...................................................................3-14
L2 Cache Support......................................................................................3-14
ECC...................................................................................................................3-14
Cycle Types...............................................................................................3-15
Error Reporting..........................................................................................3-15
Error Logging ............................................................................................3-18
ROM/Flash Interface ........................................................................................3-18
Refresh/Scrub....................................................................................................3-22
Blocks A and/or B Present, Blocks C and D Not Present .........................3-22
Blocks A and/or B Present, Blocks C and/or D Present............................3-23
Chip Defaults....................................................................................................3-24
External Register Set ........................................................................................3-24
CSR Accesses ...................................................................................................3-24
Programming Model ................................................................................................3-25
CSR Architecture..............................................................................................3-25
Register Summary.............................................................................................3-30
Detailed Register Bit Descriptions ...................................................................3-32
Vendor/Device Register ............................................................................3-32
Revision ID/General Control Register ......................................................3-33
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