NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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Table 88. LF receiver ID register (LFID) (address $0027)
Bit 7 6 5 4 3 2 1 0
R
W
ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8
Reset U U U U U U U U
POR ($00) 0 0 0 0 0 0 0 0
LFR soft
reset ($00)
0 0 0 0 0 0 0 0
Table 89. LFID register field descriptions
Field Description
7:0
ID
These two 8-bit read/write registers hold one of two ID values for LF messages. The type of ID checking can
be selected or disabled by using the IDSEL[1:0] bits in the LFCTL1 register. When ID checking is enabled
(LFIDIE = 1), the ID value received through the LFR must match the contents of the LFIDH and/or LFIDL
registers depending on the IDSEL bits in order to generate the MCU wake-up and set the LFIDF flag. If
the error detection interrupts are not enabled, LFERIE = 0, an ID mismatch will be ignored and the MCU
will remain in standby mode to minimize power consumption. If the error detection interrupts are enabled,
LFERIE = 1, an ID mismatch will trigger an interrupt to wake up the MCU, and set the set the LFERF flag.
$0000 = Result of power on or LFR reset. Existing state remains after all other reset types.
10.15.17.8 LF receiver control E register (LFCTRLE)
Table 90. LF receiver control E register (LFCTRLE) (address $0028)
Bit 7 6 5 4 3 2 1 0
R
W
reserved reserved reserved reserved TRIMEE AZSC2 AZSC1 AZSC0
Reset U U U U U U U U
POR ($01) 0 0 0 0 0 0 0 1
LFR soft
reset ($01)
0 0 0 0 0 0 0 1
Table 91. LFCTRLE register field descriptions
Field Description
3
TRIMEE
TRIMEE – TRIM Edition Enable, controls write access to the TRIM1 and TRIM2 registers.
0 = TRIM registers are read-only mode; Result of power on or LFR reset. Existing state remains after all
other reset types.
1 = TRIM registers are read/write access mode.
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