NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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Field Description
3
ADPC3
ADPC3 - Connects PTB0 to ADC MUX channel 3
0 = default PTB0 port operation, Result of Reset
1 = PTB0 connected to ADC MUX channel 3
10.18 Serial peripheral interface (SPI) module
The SPI module is configured as a standard slave SPI which allows a full duplex,
synchronous, serial communication between the unit and a master SPI device.
The principal features of the SPI block are summarized as follows:
• Slave only mode operation.
• Full-duplex, 4 wire, synchronous, serial communication.
• Command-Response communication format.
• SCLK operation up to 10 MHz supported.
• Fixed Clock polarity and phase supported (CPOL=0, CPHA = 0).
– The SPI module requires that the base clock value be low (CPOL = 0) with data
captured on the rising edge of the clock and data propagated on the falling edge of
the clock (CPHA = 0).
• Supports 8-bit register read and write operations via 16 clock transfers.
• Even Parity error-checking.
• Alternate bus master for the system-on-chip (SoC) internal IP Bus system.
– SPI can be used to access the entire Memory map of the NTM88.
• Contains eight, 8-bit memory mapped registers for user and test mode operations.
As a slave, the SPI interface is compatible with SPI interface mode 00, corresponding
to CPOL = 0 and CPHA = 0. For CPOL = 0, the idle value of the clock is zero, and the
active value of the clock is 1. For CPHA = 0, data is captured on the clock's rising edge
(low to high transition) and data is propagated on the clock’s falling edge (high to low
transition).
As a slave, the SS_B pin is driven low at the start of a transaction, held low for the
duration of the transfer, and then driven high again after the transaction is completed.
During a transaction, the master toggles the clock (SCLK). The SCLK polarity is defined
as having an idle value that is low, and an active phase that is high (CPOL = 0). Serial
input and output data is captured on the clock's rising edge and propagated on the falling
edge (CPHA = 0). Single-byte read and single-byte write operations are completed
in two strobes of SS_B of 16 SCLK cycles each; multiple byte reads and writes are
completed in additional multiples of 16 SCLK cycles. The first SCLK cycle latches the
most significant bit on MOSI to select whether the desired operation is a read (R/W = 1)
or a write (R/W = 0). The following 13 SCLK cycles are used to latch the slave register
read or write address. The final two SCLK cycles are used to latch the parity calculation
results.
When memory has been secured by SEC[1:0] settings, the SPI may access only the
address ranges $0000 to $008F and $1800 to $188F. Other access attempts will result in
an error status as defined below.
Note: The SPI and the MCU share the internal address, data, and control bus, and are
arbitrated such that the SPI will take priority over the MCU. Care must be taken by the
user application to account for inhibited execution of MCU instructions during the time
that the SPI has taken control of the internal bus.
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