NXP Semiconductors
UM11227
NTM88 family of tire pressure monitor sensors
UM11227 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User manual Rev. 6 — 24 April 2020
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10.25 Free running counter (FRC) module
The Free Running Counter (FRC) module includes an interrupt, triggered when a
programmed target value has been reached (or exceeded).
Once the FRC has been enabled, the FRC will run continuously and will roll over when
not halted. The user application may benefit from being able to program a predicted
future value into the compare register, then executing other processes until interrupted.
The interrupt event results from the value of the FRC_TIME[15:0] becoming equal to
the FRC_COMP[15:0] compare register. An interrupt vector is allocated to the FRC
comparison event.
FRC_COMP_EN will enable or disable the target comparison interrupt function. Writing
1 enables the comparison interrupt, and writing 0 disables the comparison interrupt.
Reading FRC_COMP_EN returns its present state. As the FRC may be programmed
to operate during all modes, the FRC comparison function and interrupt operate in all
modes when enabled. Writing 1 to FRC_COMP_IACK clears a new FRC_IF. Writing 0 to
the FRC_COMP_IACK has no effect.
Reading the FRC_COMP_IACK bit has no effect. If FRC_IF is 1, this indicates the
comparison function, or that the FRC_COMP_IACK has been written to 1.
Due to the FRC being powered by the 'always on' internal supply, the interrupt function,
when enabled, may generate continuous interrupts when the FRC timer registers are
equal or greater than the FRC compare registers. This condition could exist, for example,
if the FRC timer has rolled-over and the FRC compare registers are remaining at a lower
value. To prevent unwanted subsequent interrupts, users must immediately disable the
interrupt function.
To set up the next interrupt interval, users should:
• Clear and halt the FRC timer by simultaneously writing FRC_EN_HALT=0 and
FRC_CLR=1 in a single write.
• Poll the FRC_EN_HALT bit until the transition from 1 to 0
• Write the next target value into the FRC COMP registers
• Clear the interrupt status by writing 1 to the FRC_COMP_IACK bit
• Enable the FRC timer by writing 1 to the FRC_EN_HALT bit
• Poll the FRCTIMERL least significant bit until a transition from 1 to 0
• Enable the interrupt by writing 1 to the FRC_COMP_EN bit
10.25.1 Clearing or halting the FRC
Clearing or halting of the FRC, for example programming FRC_CLR to 1 or
FRC_EN_HALT to 0, simultaneously disables the comparison interrupt function, i.e. force
FRC_COMP_EN to 0. Users are to be aware that halting or restarting the FRC from a
default value disturbs the real time until the comparison condition occurs, and therefore
requires a new compare value to be calculated and written, and a new enable of the
comparison interrupt function.
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